Mode Register Output Circuit for Semiconductor Memory
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Solution Overview
Problem
Conventional semiconductor memory devices face data collision issues when issuing read and mode register read commands at minimum intervals, complicating controller-side control due to the mode signal interfering with the data input/output circuit.
Innovation Solution
A semiconductor memory device design where the mode signal from the register is output onto a data bus separate from the data input/output circuit, allowing continuous issuance of read and mode register read commands without data collision by ensuring the mode signal does not intervene in the data path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the mode signal is supplied through the data input/output circuit, then the existing data path can be used, but data collision occurs between read data and mode signal
Solution Approach 1:
The patent segments the data path into two separate channels: one for read data (through the data amplifier and data input/output circuit) and another for mode signals (through a dedicated mode signal output circuit). This segmentation prevents data collision by ensuring that mode signals and read data do not share the same transmission path, thereby maintaining signal integrity while preserving the existing data path structure.
2Reliability
If a waiting period is introduced after read command to prevent data collision, then data collision is avoided, but command issuance interval increases
Solution Approach 1:
The patent introduces a dedicated mode signal output circuit as an intermediary component that handles mode signal transmission separately from the read data path. This intermediary enables continuous command issuance at minimum intervals without data collision, as the mode signals are transmitted through a separate channel that does not interfere with read data, thereby maintaining both signal integrity and high command issuance rate.
3Reliability
If mode register read command is handled as exception, then data collision is prevented, but controller-side control becomes complicated
Solution Approach 1:
By segmenting the signal transmission paths and providing a dedicated mode signal output circuit, the patent enables the controller to issue mode register read commands using the same simple timing rules as ordinary read commands. The separation of paths ensures that no special exception handling is needed, maintaining both data signal integrity and controller control simplicity.
Data Source
AI summary
To provide a semiconductor memory device including a mode register in which a mode signal is set, a data amplifier that amplifies read data read from a memory cell array, a data bus onto which the read data amplified by the data amplifier is transmitted, a data input/output circuit that outputs a signal on the data bus to outside, and a mode signal output circuit that outputs the mode signal set in the mode register onto the data bus. Because the mode signal is not caused to interrupt halfway along the data input/output circuit, but supplied onto the data bus that connects the data amplifier to the data input/output circuit, no collision of the read data with the mode signal occurs in the data input/output circuit.