Mode-Selecting Apparatus for Accurate Synchronization Signal Detection
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Solution Overview
Problem
Conventional liquid crystal display devices face challenges in accurately judging synchronization signals when only VSC and DE signals are input, or when either VSC or HSC signals are not input, leading to inaccurate synchronization detection and increased circuit size for dot clock counting.
Innovation Solution
A mode-selecting apparatus that counts input HSC and DE signals in each frame period and selects between a first mode using VSC and HSC signals or a second mode using the DE signal, based on the number of signals received, to accurately determine the synchronization signal as a reference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the liquid crystal display device counts a number of dot clocks received in a high level period or a low level period of the VSC signal to judge whether the VSC signal, the HSC signal or the DE signal is input, then the device can identify synchronization signals, but the circuit size of a counter for counting a number of dot clocks is unavoidably increased
Solution Approach 1:
The patent extracts the dot clock counting function from the main synchronization detection circuit and implements it separately in the detection unit. This allows the main timing controller to operate with simplified logic while the detection unit handles the complex counting and comparison operations independently, thereby reducing the overall circuit complexity while maintaining detection accuracy
Solution Approach 2:
The patent introduces an intermediary detection unit that acts as a mediator between the input signals and the timing controller. This detection unit performs the complex dot clock counting and synchronization signal identification, then provides simplified mode selection signals to the timing controller, thereby reducing the burden on the main controller circuit
2Stability of the object's composition
If the liquid crystal display device carries out the detection of synchronization in accordance with the VSC and HSC signals even when a DE signal is input, then the device maintains consistent detection methodology, but it fails to accomplish the detection of synchronization when only DE signal or combination of one synchronization signal and DE signal is input
Solution Approach 1:
The patent implements dynamic detection methodology that automatically adapts to different signal input combinations. The detection unit counts dot clocks during specific periods and compares the counts against reference values to dynamically determine whether VSC, HSC, or DE signals are present, allowing the system to maintain stable operation across various input scenarios without requiring manual configuration
Solution Approach 2:
The patent creates a universal detection mechanism that can handle multiple signal input combinations (VSC only, HSC only, DE only, or any combination thereof) through a single unified detection unit. This detection unit performs dot clock counting and comparison operations that work regardless of which specific signals are input, making the synchronization detection system universally applicable to different signal configurations
3Adaptability or versatility
If the liquid crystal display device receives only VSC and DE signals or only HSC and DE signals, then the device operates with partial synchronization signals, but it cannot accurately judge a synchronization signal as a reference signal
Solution Approach 1:
The patent performs preliminary dot clock counting during specific high or low level periods of the VSC signal before making synchronization detection decisions. By pre-counting the dot clocks and comparing them against reference values, the system establishes a baseline that enables accurate identification of the actual synchronization signals even when only partial signal combinations are input, thereby ensuring accurate reference signal judgment
Data Source
AI summary
A mode-selecting apparatus for selecting one of a first mode in which images are displayed on a display unit in accordance with a vertical synchronization control signal and a horizontal synchronization control signal, and a second mode in which images are displayed on the display unit in accordance with a data-enable signal, includes a first unit which counts a number of input horizontal synchronization control signals in each of frame periods, a second unit which counts a number of input data-enable signals in each of frame periods, and a third unit which selects one of the first and second modes in accordance with both the number of input horizontal synchronization control signals and the number of input data-enable signals.