Model-Based OPC for Semiconductor Mask Fabrication
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Solution Overview
Problem
Conventional rule-based optical proximity effect correction (OPC) techniques in semiconductor device fabrication are limited in accuracy and cannot detect weak process windows, leading to defects in the mask layout that cannot be repaired, resulting in unusable circuit patterns and limitations in detecting weak process windows for semiconductor devices.
Innovation Solution
The method involves generating an optical model before fixing the mask layout, allowing for lithography-friendly layout (LFL) circuit patterns to be created, which are then corrected using model-based OPC to produce OPC circuit patterns, enabling the fabrication of semiconductor devices with improved accuracy and defect prevention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If rule-based OPC is performed after full chip layout is fixed, then the layout can be completed, but defects cannot be detected or repaired and the OPC accuracy is limited
Solution Approach 1:
The patent applies preliminary action by performing model-based OPC and generating optical models before the full chip layout is finalized. This allows defects to be detected and corrected in the layout design phase rather than after fabrication, enabling repair of layout defects and improvement of pattern transfer accuracy simultaneously
Solution Approach 2:
The patent implements feedback by using generated optical models to predict and analyze potential defects in the circuit pattern before manufacturing. This feedback mechanism allows the layout to be refined and corrected based on predicted performance, improving both defect detection capability and pattern accuracy
2Manufacturing precision
If model-based OPC is used to correct the circuit pattern, then the accuracy of correction is high, but a large amount of computation is needed
Solution Approach 1:
The patent applies segmentation by dividing the full chip into multiple regions or blocks for separate optical model generation and analysis. This allows the computational task to be divided into smaller, more manageable segments that can be processed efficiently while maintaining high correction accuracy for each segment
Solution Approach 2:
The patent performs preliminary optical model generation and analysis on representative samples or critical regions before finalizing the complete chip layout. This preliminary action identifies critical areas requiring high-precision OPC while reducing overall computation by focusing resources on the most critical patterns
Data Source
AI summary
Design rules for circuit patterns of a semiconductor device are identified, and schematic layouts of the circuit patterns are generated according to the design rules. Lithography friendly layout (LFL) circuit patterns are generated from the schematic layouts. Target layout circuit patterns are generated from the LFL circuit patterns. Optical proximity effect correction (OPC) is performed on the target layout circuit patterns to generate OPC circuit patterns. A mask is fabricated from the OPC circuit patterns, and may be used fabricate a semiconductor device.