Model-Based IC Routing for Thickness Variation Control
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Solution Overview
Problem
Conventional electronic design automation (EDA) systems fail to account for manufacturing variations during integrated circuit (IC) layout, floorplanning, and routing, leading to issues such as thickness variations that cause operational failures, increased power consumption, and yield problems.
Innovation Solution
A model-based method for layout, floorplanning, and routing that uses manufacturing models to guide the placement and routing of polygons, analyzing parameters like thickness variations to optimize routes and ensure manufacturability, potentially reducing or eliminating the need for Design Rule Check (DRC) processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional EDA systems perform layout and routing without manufacturing models, then design productivity is improved, but manufacturing precision deteriorates due to unaccounted thickness variations
Solution Approach 1:
The patent applies preliminary action by performing model-based analysis during the design phase to predict manufacturing variations before fabrication. The system analyzes the layout design using manufacturing models to identify potential thickness variation issues early, allowing designers to modify the design proactively rather than reacting to manufacturing problems later. This preliminary assessment integrates manufacturing constraints into the design process itself.
Solution Approach 2:
The patent implements feedback by using manufacturing models to provide predictive information about thickness variations back to the design process. The system continuously refines the layout design based on model predictions of manufacturing outcomes, creating a closed-loop process where manufacturing feedback informs design iterations. This feedback mechanism allows the design to be optimized for actual manufacturing performance rather than idealized conditions.
2Manufacturing precision
If model-based analysis is performed during routing, then manufacturing precision is improved, but device complexity increases due to additional processing requirements
Solution Approach 1:
The patent uses manufacturing models as an intermediary between the layout design and the actual manufacturing process. These models serve as a predictive layer that translates design geometry into expected manufacturing outcomes, allowing the EDA system to make informed routing decisions without directly controlling the manufacturing equipment. The intermediary models bridge the gap between design intent and manufacturing reality, simplifying the overall process by providing predictive guidance.
Solution Approach 2:
The patent applies parameter changes by adjusting routing decisions based on predicted thickness variations. The system modifies routing parameters such as wire placement, spacing, and layer selection in response to model predictions about where thickness variations are likely to occur. This dynamic parameter adjustment allows the design to adapt to manufacturing realities without requiring complete redesign of the manufacturing process itself.
3Ease of operation
If conventional routing is performed without manufacturing considerations, then ease of operation is improved, but reliability deteriorates due to operational failures from thickness variations
Solution Approach 1:
The patent applies preliminary action by identifying and addressing potential reliability issues during the routing phase itself. The system uses manufacturing models to predict where thickness variations may cause operational failures, and modifies the routing design proactively to avoid these problem areas. This preliminary identification and correction of reliability issues prevents failures before they occur, rather than requiring post-manufacturing testing and repair.
Data Source
AI summary
Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.