Hardware Model Calculation Unit for Real-Time Neural Network Processing
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Solution Overview
Problem
Existing data-based models, such as multilayer perceptron models, require high computing capacity for real-time calculations in control devices due to the large number of support points needed for precision, making them difficult to implement in systems like internal combustion engines and electric drives.
Innovation Solution
A hardware-based model calculation unit is designed to calculate neuron layers of a multilayer perceptron model, featuring a processor core, memory for configuration and data storage, and a DMA unit to efficiently process input and output quantities, reducing computational load and enabling real-time calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data-based models with large number of support points are used to achieve adequate modeling precision, then measurement precision is improved, but computing capacity requirement increases
Solution Approach 1:
The model calculation is divided into multiple neuron layers, where each layer processes a subset of the computation. The DMA unit segments the data transfer operations, moving data in blocks between memory and processing units rather than individual elements, thereby reducing overhead and enabling the system to handle larger models with more support points while maintaining real-time performance.
2Measurement precision
If data-based models with large number of support points are used to achieve adequate modeling precision, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The model calculation unit is designed as a universal hardware architecture that can compute different data-based models (Gauss process models, multi-layer perceptron models, and other neural network models) using the same underlying computational engine. The DMA unit and memory structure are configured to handle various model types, reducing the need for multiple specialized devices and thereby managing complexity while supporting high-precision modeling.
3Productivity
If hardware realization of model calculation unit is provided to enable real-time calculation, then productivity is improved, but device complexity increases
Solution Approach 1:
The processor core and DMA unit are merged into an integrated model calculation unit with shared memory structures. The configuration memory and data storage region are combined within the same hardware module, allowing tight coupling between data movement and computation. This integration reduces the complexity that would arise from separate components while enabling real-time performance through optimized data flow and reduced communication overhead.
4Productivity
If successive calculation of multiple neuron layers is implemented, then productivity is improved, but loss of time increases due to data transfer
Solution Approach 1:
The DMA unit operates continuously to transfer data between memory and the processor core during the successive calculation of neuron layers. Rather than completing one layer entirely before transferring data, the system maintains continuous data flow, prefetching inputs for the next layer while the current layer is being processed. This overlapping of computation and data transfer eliminates idle time and maintains high productivity across multiple layers.
Data Source
AI summary
A hardware-implemented multi-layer perceptron model calculation unit includes: a processor core to calculate output quantities of a neuron layer based on input quantities of an input vector; a memory that has, for each neuron layer, a respective configuration segment for storing configuration parameters and a respective data storage segment for storing the input quantities of the input vector and the one or more output quantities; and a DMA unit to successively instruct the processor core to: calculate respective neuron layers based on the configuration parameters of each configuration segment, calculate input quantities of the input vector defined thereby, and store respectively resulting output quantities in a data storage segment defined by the corresponding configuration parameters, the configuration parameters of configuration segments successively taken into account indicating a data storage region for the resulting output quantities corresponding to the data storage region for the input quantities for a subsequent neuron layer.