Model Checker for Eliminating Illegal States in Equivalence Checking
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Solution Overview
Problem
Transaction equivalence checking in semiconductor design verification often results in false non-equivalence due to illegal starting states, which are computationally intensive to identify and verify, especially in complex modern designs.
Innovation Solution
A method that uses a model checker to determine if the starting states of design representations are legal, allowing for the generation of generalized constraints to eliminate illegal states and reduce computational power by only checking for legality when mismatches occur, enabling demand-driven removal of spurious mismatches and arbitrary starting states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transaction equivalence checking is performed on complex semiconductor designs, then verification completeness is improved, but computational resource consumption increases significantly
Solution Approach 1:
The patent applies preliminary action by performing reachability analysis on starting states before conducting transaction equivalence checking. The model checker evaluates whether starting states are legal (reachable from reset states) in advance, eliminating illegal states before the main verification process. This preliminary filtering reduces the computational burden during actual equivalence checking while maintaining verification completeness.
2Measurement precision
If all starting states are checked for legality in transaction equivalence checking, then false non-equivalence is eliminated, but verification time increases
Solution Approach 1:
The patent applies partial action by selectively checking only those starting states that are actually reached during transaction equivalence checking, rather than checking all possible starting states. The model checker is invoked on-demand when mismatches occur, and generalized constraints are generated to eliminate entire classes of illegal states. This partial checking approach maintains mismatch detection accuracy while significantly reducing verification time.
3Productivity
If generalized constraints are generated to eliminate illegal states, then spurious mismatches are reduced, but model checker complexity increases
Solution Approach 1:
The patent applies self-service by having the model checker automatically generate generalized constraints from illegal states discovered during equivalence checking. The system autonomously identifies patterns in illegal states and creates constraints that prevent their recurrence, without requiring manual intervention. This automation improves equivalence checking efficiency while the model checker manages its own complexity through systematic constraint generation.
Data Source
AI summary
A method for equivalence checking includes obtaining a first and a second representation for a semiconductor design and applying a set of inputs to both representations. The outputs of the first representation are compared to the outputs of the second representation. If a mismatch is found, the starting states for the first and second representations are evaluated using a model checker to see if they are reachable from a known legal state such as reset state for that representation. If both of the starting states are reachable, the mismatch is a real mismatch providing a counter-example of the equivalence of the two representations. If one or both of the starting states are unreachable, the mismatch is a spurious mismatch and the model checker can be used to generate an invariant to preclude those starting states in future iterations of the equivalence checker.