Model Order Reduction for Electronic Circuit Characterization
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Solution Overview
Problem
Conventional methods for characterizing modern electronic circuits, especially wireless communication chips, are time-consuming and computationally intensive due to the need for small time steps and complex simulations, exacerbating the challenge of spectral regrowth outside allowed bandwidths, particularly in 5G/LTE circuits with millions of components.
Innovation Solution
The implementation of a model order reduction (MOR)-based envelope Fourier technique with harmonic balance formulation allows for reduced order training models, using larger time steps and stability-preserving projections to characterize electronic circuits efficiently, reducing computational resources while maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional simulation methods are used to characterize electronic circuits, then measurement precision and reliability are maintained, but simulation time and computational resources increase dramatically
Solution Approach 1:
The patent segments the full simulation process into training and validation phases. Training models are created at selected time points using conventional accurate methods, then model order reduction is applied to these training models. The reduced models are validated against full simulations at different time points, allowing accurate characterization without running full simulations at all times.
Solution Approach 2:
The patent performs preliminary action by creating reduced order models in advance during the training phase. These pre-computed reduced models capture the essential circuit behavior and can be used for rapid validation and analysis without requiring time-consuming full simulations when needed.
2Productivity
If model order reduction is applied to reduce computational burden, then simulation time decreases, but measurement precision may deteriorate
Solution Approach 1:
The patent implements feedback by validating the reduced order models against full simulations at multiple time points. The validation process compares results from reduced models with those from conventional simulations, ensuring that the reduced models maintain sufficient accuracy for their intended purpose while achieving significant speedups.
Solution Approach 2:
The patent creates time-varying reduced order models that adapt to different operating conditions. By selecting training time points that represent different circuit states and creating reduced models for each, the system maintains accuracy across varying conditions while preserving computational efficiency.
3Measurement precision
If full system simulations are performed to ensure accuracy, then measurement precision is maintained, but device complexity and computational resources increase
Solution Approach 1:
The patent extracts the essential dynamic behavior of the complex circuit system into reduced order models. By identifying and capturing only the dominant modes and time-varying characteristics, the method removes unnecessary complexity from the full system model while retaining the essential behavior needed for accurate validation and analysis.
Data Source
AI summary
Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at least model order reduction of the MOR-based envelope Fourier technique to the training model. A time varying system may be determined for the electronic circuit based by using at least the reduced order training model.