High-Level Model Power Optimization via Rate Region Transmutation
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Solution Overview
Problem
Existing power consumption analyzers for hardware devices like PLDs, FPGAs, and ASICs primarily operate at the Register Transfer Level (RTL) and are tightly coupled to specific target hardware, limiting their ability to effectively manage power consumption at higher levels and independently assess dynamic and static power sources.
Innovation Solution
A system that computes power information for high-level models, allowing transmutations to reduce power consumption by moving components between rate regions, reducing bit width, and sharing resources, using a compiler, power score evaluation engine, and optimization tools to generate optimized hardware description language code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If power consumption analyzers operate at the Register Transfer Level (RTL) and are tightly coupled to specific target hardware, then they can provide target-specific power analysis, but they cannot effectively manage power consumption at higher levels or independently assess power sources
Solution Approach 1:
The system segments power analysis into two distinct components: a high-level model evaluator that operates independently of target hardware, and a target-specific hardware description generator. The high-level model is divided into functional components with associated power parameters, allowing independent assessment before target implementation. This segmentation enables the system to provide versatile power analysis across different hardware targets without requiring complex target-specific analysis logic in the high-level model.
Solution Approach 2:
The patent introduces an intermediary high-level model with power parameters that acts as a mediator between the design specification and target hardware implementation. This intermediary model contains power-related information independent of any specific target, allowing the system to assess power sources (dynamic and static) independently before generating target-specific hardware descriptions. The intermediary model serves as a bridge that enables both high-level power assessment and target-specific optimization.
2Loss of energy
If components are moved between rate regions to reduce power consumption, then dynamic power can be reduced, but the model complexity increases
Solution Approach 1:
The system applies dynamics by enabling components to change their operational rate dynamically. Components can be moved between different rate regions (fast rate and slow rate) based on power optimization requirements. The hardware description generator creates rate transition logic that allows components to switch between operational speeds, reducing dynamic power consumption when full speed is not required. This dynamic rate adjustment provides a mechanism to reduce power without permanently increasing model complexity.
Solution Approach 2:
The patent changes the operational parameter of components by adjusting their rate of operation. The high-level model specifies power parameters including operational rate, and the hardware description generator translates these into concrete rate transitions. By changing the operational rate parameter of components, the system can reduce dynamic power consumption (which is proportional to switching frequency) while maintaining the same functional behavior. This parameter adjustment approach provides a systematic way to reduce power without fundamental model redesign.
3Loss of energy
If bit width of data or signals is reduced, then power consumption decreases, but the manufacturing precision or data representation accuracy may be compromised
Solution Approach 1:
The system changes the bit width parameter of data signals as an optimization variable. The high-level model specifies data widths, and the hardware description generator can reduce these widths based on actual operational requirements analyzed from the model behavior. By analyzing the range and precision requirements of signals, the system can reduce bit width from the original specification to a minimal sufficient width, reducing power consumption (which is proportional to the number of transistors and switching activity) while maintaining the precision needed for correct operation.
4Loss of energy
If multiple instances of a resource are reduced in favor of a shared resource, then power consumption and device area are reduced, but the access time and control complexity increase
Solution Approach 1:
The system merges multiple instances of the same resource into a single shared resource. The hardware description generator identifies redundant resource instances in the high-level model and consolidates them into shared resources with appropriate multiplexing logic. This merging reduces the total number of resource instances, thereby reducing power consumption (fewer active components) and device area. The generator includes control logic to manage access to the shared resource, coordinating multiple consumers to prevent conflicts and maintain correct operational timing.
Solution Approach 2:
The patent applies universality by designing shared resources that serve multiple functions and multiple consumers. A single resource instance is designed to handle operations for multiple different consumers through time-multiplexed access. The hardware description generator creates universal resource structures that can be accessed by multiple parts of the design, reducing the need for dedicated resources for each consumer. This multi-functional approach reduces overall resource count and power consumption while maintaining the operational requirements of all consumers through proper access arbitration.
Data Source
AI summary
A system and method evaluates power information for a high-level model to be implemented in target hardware, and performs one or more power-reducing transmutations on the model. Transmutations may include moving one or more components from a fast rate region to a slow rate region, reducing bit width of data, signals, or other values, and replacing multiple instances of a resource with a shared instance of the resource. An in-memory representation of the model may be generated that reduces the model to a plurality of core components. A power score evaluation engine may assign power scores to the core components. Power scores may be retrieved from one or more power score database. The power scores may be non-dimensional scores representing power consumption relationships among the core components, and be target independent. Hints or alerts regarding suggested changes to the model to optimize power consumption may be presented to a user. A revised model incorporating the suggested changes may be constructed. The one or more transmutations resulting in a lowest total power score may be selected for hardware generation.