Modeless 32-bit and 64-bit Addressing via Load/Store Unit
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Solution Overview
Problem
MIPS 64-bit architectures face challenges in supporting 32-bit binaries without requiring a mode bit, as providing separate instructions for 64-bit and 32-bit memory access instructions consumes significant operation code space and is cumbersome for programmers and development environments.
Innovation Solution
A processor architecture that can execute instructions in both privileged and unprivileged modes, using a configurable load/store unit to determine whether register values are single-word or double-word sized without needing a mode bit, allowing seamless execution of 32-bit code on 64-bit machines by interpreting register values within pre-defined address ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate instructions are provided for 64-bit and 32-bit memory access operations, then the processor can support both address ranges, but the operation code space is significantly consumed and the architecture becomes complex
Solution Approach 1:
The load/store instruction is designed to perform both 32-bit and 64-bit memory access operations using a single unified instruction format. The instruction uses general purpose registers that can hold values interpreted as either single-word (32-bit) or double-word (64-bit) immediate values, eliminating the need for separate instruction sets for different address ranges.
Solution Approach 2:
The processor dynamically determines whether to interpret register values as 32-bit or 64-bit based on the calculated effective address. The load/store unit checks if the address falls within the lower 32-bit range or upper 32-bit range of the 64-bit address space, and automatically adjusts the interpretation of register values accordingly, allowing modeless operation between 32-bit and 64-bit addressing.
2Adaptability or versatility
If a mode bit is used to switch between 32-bit and 64-bit execution modes, then the processor can manage different address ranges, but the execution requires privileged code intervention at boundaries which reduces efficiency
Solution Approach 1:
The load/store unit autonomously determines the appropriate address interpretation without requiring external control from a mode bit or privileged code. The unit calculates the effective address and self-determines whether the register value should be treated as a 32-bit or 64-bit immediate value based on the address range, enabling seamless execution across boundary conditions without mode changes.
3Device complexity
If general purpose registers are used as both single-word and double-word immediate values, then code space is optimized, but the processor must determine the correct interpretation without mode bits
Solution Approach 1:
The effective address calculation acts as an intermediary that resolves the ambiguity of register value interpretation. By first calculating the effective address using the register value and immediate offset, the system can determine whether the address falls in the lower or upper 32-bit range, which then informs the correct interpretation of the register value as either single-word or double-word sized.
Data Source
AI summary
In an aspect, a processor supports modeless execution of 64 bit and 32 bit instructions. A Load/Store Unit (LSU) decodes an instruction that without explicit opcode data indicating whether the instruction is to operate in a 32 or 64 bit memory address space. LSU treats the instruction either as a 32 or 64 bit instruction in dependence on values in an upper 32 bits of one or more 64 bit operands supplied to create an effective address in memory. In an example, a 4 GB space addressed by 32-bit memory space is divided between upper and lower portions of a 64-bit address space, such that a 32-bit instruction is differentiated from a 64-bit instruction in dependence on whether an upper 32 bits of one or more operands is either all binary 1 or all binary 0. Such a processor may support decoding of different arithmetic instructions for 32-bit and 64-bit operations.