Cellular Modem ADC Timing Using Synchronized Clock Offset Measurement
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Solution Overview
Problem
Current wireless modems face uncertainty in Analog-to-Digital Converter (ADC) timing due to accumulated delay in the ADC input clock generation path, affecting the accuracy of RF signal measurements and positioning in mobile communication networks.
Innovation Solution
The introduction of a switch at the ADC input terminal to route the system clock directly for timing determination and the use of an ADC output timing determining module with a counter to calculate the time difference between the system clock and ADC output clock, ensuring accurate ADC output timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ADC input clock generation path is used for timing, then the ADC can capture analog signals, but accumulated delay in the clock generation path causes timing uncertainty and reduces measurement accuracy
Solution Approach 1:
The patent separates the timing determination function from the signal capture function by introducing a dedicated system clock path that is independent of the ADC input clock generation path. This segmentation allows the system clock to provide accurate timing references without being affected by the delays in the ADC clock generation chain.
Solution Approach 2:
The patent introduces a counter as an intermediary device that measures the time difference between the system clock and ADC output clock. This counter acts as a mediator to quantify and compensate for the timing offset, enabling accurate timing determination despite the accumulated delay in the ADC clock path.
2Measurement precision
If a dedicated timing determination path is introduced, then ADC output timing accuracy is improved, but device complexity increases due to additional components
Solution Approach 1:
The system clock serves multiple functions: it provides the reference timing for the entire system and simultaneously serves as the basis for determining ADC output timing. This multi-functionality reduces the need for separate dedicated timing components, thereby limiting the increase in device complexity.
3Measurement precision
If the system clock is synchronized with the start signal and used to generate capturing sample clock, then timing accuracy is improved, but the processing steps and device complexity increase
Solution Approach 1:
The patent combines the start signal generation and capturing sample clock generation into a unified process that is synchronized with the system clock. By merging these functions and coordinating them through the common system clock reference, the patent reduces the need for separate synchronization mechanisms, thereby limiting the increase in device complexity.
Data Source
AI summary
An analog-to-digital converter (ADC) has been disclosed. In some implementations, the ADC is configured to generate ADC samples based on input signals and an ADC input clock. The ADC is further configured to generate at a first time point a synchronized start signal indicating a starting point of capturing the ADC samples. The start signal and a system clock can be synchronized at a second time point. At a third time point, a capturing sample clock for capturing the ADC samples is generated. The synchronized start signal and the capturing sample clock can be input to a counter to determine a time difference between the second and third time points. An ADC output timing of the ADC samples can be determined based on the time difference.