Multi-Core Modem Board Latency Control via Interrupt Routing
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Solution Overview
Problem
SMP Linux with PREEMPT RT patch, used in multi-core processors for LTE wireless base stations, experiences unbounded latency spikes due to its non-hardcore real-time operating system characteristics, which can impair the system's ability to meet stringent real-time performance needs, particularly affecting the LTE Layer 2 scheduler.
Innovation Solution
Disabling non-essential interrupts on data plane cores and routing them to the control plane core, while running hardware components like the queue manager in polling mode instead of interrupt mode, to reduce latency and enhance real-time performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SMP Linux with PREEMPT RT is used on multi-core processors for LTE base stations, then multi-cell support and cost reduction are achieved, but unbounded latency spikes occur that impair real-time performance
Solution Approach 1:
The system segments processor cores into control plane cores and data plane cores, with each type dedicated to specific functions. Control plane cores handle non-real-time tasks while data plane cores handle real-time LTE Layer 2 processing, preventing cross-interference and ensuring deterministic real-time performance while supporting multiple cells.
Solution Approach 2:
Non-essential interrupts are extracted from data plane cores and routed to control plane cores. This separation removes sources of latency spikes from the real-time processing path, allowing the data plane to maintain bounded latency while the control plane handles less time-critical interrupt processing.
2Reliability
If multiple modem boards are used to support multi-cell configurations, then real-time performance is maintained, but system complexity and cost increase
Solution Approach 1:
Multiple cell processing capabilities are merged onto a single modem board using multi-core processors. The board consolidates what previously required separate physical boards, reducing system complexity and cost while maintaining real-time performance through dedicated data plane cores and interrupt routing strategies.
Solution Approach 2:
The modem board is designed with universal multi-cell support through multi-core processors that can handle multiple LTE cells simultaneously. The architecture allows a single board to perform functions that previously required multiple specialized boards, achieving versatility without sacrificing real-time performance.
3Speed
If hardware components run in interrupt mode, then responsiveness is improved, but latency spikes increase due to excessive interrupts on data plane cores
Solution Approach 1:
The control plane core acts as an intermediary for non-essential interrupt processing. Instead of data plane cores directly handling all interrupts, the system routes non-critical interrupts through the control plane, which mediates between hardware events and real-time processing needs, reducing latency spikes while maintaining responsiveness through selective interrupt handling.
Data Source
AI summary
A system for providing multi-cell support within a single SMP partition in a telecommunications network is disclosed. The typically includes a modem board and a multi-core processor having a plurality of processor cores, wherein the multi-core processor is configured to disable non-essential interrupts arriving on a plurality of data plane cores and route the non-essential interrupts to a plurality of control plane cores. Optionally, the multi-core processor may be configured so that all non-real-time threads and processes are bound to processor cores that are dedicated for all control plane activities and processor cores that are dedicated for all data plane activities will not host or run any threads that are not directly needed for data path implementation or Layer 2 processing.