Modem Chip Internal Memory Layout for Fast Transport Block CRC

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Solution Overview

Problem

The existing communication systems face challenges in completing a second cyclic redundancy check (CRC) on decoded transport blocks within a preset time due to increased data size and bus load, caused by the external memory being shared with processors, leading to performance degradation.

Innovation Solution

A modem chip with an internal memory is used to perform a second CRC on target blocks corresponding to code blocks, storing intermediate data in the internal memory and minimizing access to the external memory, thereby reducing bus and memory burden.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the external memory is shared with processors, then memory resource utilization is improved, but bus load and access time increase causing CRC operations to exceed preset time

Engineering Contradiction:

Improvememory resource utilizationVSAvoidCRC operation time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent segments the memory system into two parts: external memory for storing decoded code blocks and internal memory for storing intermediate data during CRC operations. This segmentation allows the modem to perform CRC operations using internal memory without competing for external memory bandwidth, thus resolving the time loss issue while maintaining efficient memory utilization.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The internal memory acts as an intermediary between the modem's CRC processing and the external memory system. By introducing this intermediate storage layer, the patent enables the modem to conduct CRC operations independently without being blocked by processor activities on the external memory, thereby reducing bus load and ensuring timely CRC completion.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If data size of decoded code blocks increases, then communication capability is improved, but access to external memory increases bus load and memory load

Engineering Contradiction:

Improvedata size of decoded code blocksVSAvoidbus load and memory load

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent extracts the intermediate data storage function from the external memory system and places it in the internal memory. This extraction reduces the burden on the external memory and bus, allowing larger data sizes to be processed without proportionally increasing bus load and memory load complexity.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS20260031934A1Modem chip capable of performing cyclic redundancy check using internal memory and system on chip including the modem chip

Publication Date: 2026.01.29 SAMSUNG ELECTRONICS CO LTD

AI summary

A modem chip receives a codeword including a transport block composed of a plurality of code blocks, and includes a hybrid automatic repeat request (HARQ) processing circuit configured to perform a HARQ-based processing operation with respect to the codeword, and an internal memory configured to store data generated by the HARQ processing circuit. The HARQ processing circuit includes a code block processing circuit configured to decode the plurality of code blocks in units of code blocks and perform a first cyclic redundancy check on each of the decoded plurality of code blocks, and a codeword processing circuit configured to perform a second cyclic redundancy check on a decoded transport block.