Modified Bit Array for Cache Coherence Status
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Solution Overview
Problem
Modern microprocessors face challenges in cache line coherence status management due to increased size and power consumption when adding multiple ports to cache memory arrays, and replicating tag arrays while updating cache line status consumes bandwidth and power.
Innovation Solution
A microprocessor design that includes a data cache with a modified bit array to indicate cache line modifications, allowing the second functional unit to read this status without updating the tag array, thereby reducing traffic and simplifying floor-planning and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple ports are added to cache memory arrays to allow simultaneous access by multiple functional units, then access performance is improved, but array size and power consumption increase significantly
Solution Approach 1:
The tag array is segmented into multiple replicated instances (first tag array, second tag array, etc.), each accessible by a specific functional unit. This allows simultaneous access without requiring a single large multi-ported array, thus improving access performance while controlling array size.
Solution Approach 2:
Each tag array instance serves multiple purposes: it stores tags for cache lines accessible by its associated functional unit, and collectively they provide the functionality of a single large tag array. This multi-functionality approach improves access performance while managing array size.
2Speed
If multiple ports are added to cache memory arrays to allow simultaneous access by multiple functional units, then access performance is improved, but power consumption increases significantly
Solution Approach 1:
The tag array is segmented into multiple replicated instances, each accessible by a specific functional unit. This allows simultaneous access without requiring a single large multi-ported array, thus improving access performance while controlling power consumption through selective activation of only needed array instances.
Solution Approach 2:
Each functional unit has its own dedicated tag array instance, eliminating the need for complex arbitration and control logic that would consume power in a shared multi-ported array. The system serves itself through this decentralized architecture.
3Ease of manufacture
If tag arrays are replicated to allow single-ported access by each functional unit, then floor-planning and power management are simplified, but bandwidth consumption increases when updating cache line status
Solution Approach 1:
The modified bit status information is extracted from the tag array and stored separately in a dedicated modified bit array. This allows functional units to read status information without consuming bandwidth on the tag array, thus simplifying floor-planning while reducing bandwidth consumption for status updates.
Solution Approach 2:
A separate modified bit array acts as an intermediary between the data array and tag arrays, providing status information without requiring access to the tag arrays. This mediator approach simplifies floor-planning and reduces bandwidth consumption on tag arrays.
4Use of energy by stationary object
If tag arrays are replicated to allow single-ported access by each functional unit, then power management is simplified, but bandwidth consumption increases when updating cache line status
Solution Approach 1:
The modified bit status information is extracted from the tag array and stored separately in a dedicated modified bit array. This allows functional units to read status information without consuming bandwidth on the tag array, thus simplifying power management while reducing bandwidth consumption for status updates.
Solution Approach 2:
A separate modified bit array acts as an intermediary, providing status information without requiring access to the tag arrays. This mediator approach simplifies power management and reduces bandwidth consumption on tag arrays.
Data Source
AI summary
A microprocessor includes first and second functional units and a data cache having a data array having a write port, a modified bit array having a read port and a write port, and a tag array having a read port, each array having the corresponding predetermined organization. The first functional unit writes data to a cache line of the data array. The first functional unit sets a modified bit in the modified bit array to indicate that the corresponding cache line in the data array has been modified. The second functional unit reads the modified bit from the modified bit array to determine whether or not the cache line has been modified. The second functional unit reads a partial status of the corresponding cache line from the tag array. The partial status does not indicate whether the cache line has been modified. The tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line.