Modified Bit Array for Cache Coherence Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern microprocessors face challenges in cache line coherence status management due to increased size and power consumption when multiple functional units access cache memory, and replicating tag arrays while reducing bandwidth and power consumption issues.
Innovation Solution
A cache memory system with three arrays: one for storing cache lines, another for the first partial status, and a third for indicating modification status, allowing only the modification status to be updated in the third array, thereby reducing the need to access all tag arrays for status updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple tag arrays are replicated for each functional unit, then each functional unit can access the tag array simultaneously, but the total space required increases and power consumption increases
Solution Approach 1:
The tag array is segmented into multiple single-ported arrays, with each functional unit having its own dedicated tag array. This segmentation allows simultaneous access by different functional units while keeping each individual tag array smaller, thus reducing the complexity of accessing a single large multi-ported array.
2Productivity
If multiple tag arrays are replicated for each functional unit, then each functional unit can access the tag array simultaneously, but power consumption increases because all tag arrays must consume power during updates
Solution Approach 1:
The modified bit storage function is extracted from the tag arrays and placed in a separate dedicated array. This allows the tag arrays to remain read-only during modification operations, eliminating the need for them to consume power during write operations, while the separate modified bit array handles the write operations independently.
3Area of stationary object
If a single multi-ported tag array is used, then space is saved, but the size becomes very large making floor-planning difficult and access bandwidth is limited
Solution Approach 1:
The large single tag array is divided into multiple smaller single-ported tag arrays, each accessible by a specific functional unit. This segmentation makes floor-planning easier as each smaller array can be independently placed and managed, while still providing the required simultaneous access capability through the multiple arrays.
4Reliability
If all tag arrays are accessed to update status when cache line is modified, then coherence is maintained, but precious access bandwidth is consumed
Solution Approach 1:
The modification status tracking is extracted from the tag arrays and stored in a separate modified bit array. When a cache line is modified, only the corresponding bit in the modified bit array needs to be updated, not the entire tag arrays. This maintains coherence information while preserving tag array bandwidth for other operations.
Data Source
AI summary
A cache memory system includes a first array of storage elements each configured to store a cache line, a second array of storage elements corresponding to the first array of storage elements each configured to store a first partial status of the cache line in the corresponding storage element of the first array, and a third array of storage elements corresponding to the first array of storage elements each configured to store a second partial status of the cache line in the corresponding storage element of the first array. The second partial status indicates whether or not the cache line has been modified. When the cache memory system modifies the cache line within a storage element of the first array, it writes only the second partial status in the corresponding storage element of the third array to indicate that the cache line has been modified but refrains from writing the first partial status in the corresponding storage element of the second array. The cache memory system reads both the first partial status and the second partial status to determine the full status.