Modified 2/3 Clock Divider Stages for Glitchless Wide-Range Switching
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Solution Overview
Problem
Existing ⅔ dividers are limited in their divide ratio range and suffer from clock glitches and spurs when switching between frequencies, particularly at high input frequencies, due to the inability to completely shut off downstream stages and the additional current consumption of using divide-by-one stages.
Innovation Solution
A modified ⅔ divider stage is introduced with an additional enable input that allows downstream stages to be disabled, preventing toggling and reducing spurs, and a method to update the divide ratio without glitches by using an update clock signal from the most downstream enabled stage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If downstream stages are completely shut off to extend divide range, then divide ratio range is improved, but clock glitches and spurs occur when switching frequencies
Solution Approach 1:
The patent applies preliminary action by pre-positioning the update clock signal from the most downstream enabled stage before a divide ratio change is needed. This allows the divider to be prepared in advance for switching, ensuring that when the divide ratio changes, the transition occurs without glitches or spurs because the update mechanism is already in place and synchronized.
Solution Approach 2:
The patent implements dynamics by making the divider chain adaptable and reconfigurable. Different stages can be dynamically enabled or disabled based on the desired divide ratio, allowing the system to transition between different operational states (divide by 2, divide by 3, or disabled) without fixed limitations, thus achieving both extended range and glitch-free operation.
2Adaptability or versatility
If divide-by-one stages are used to extend divide range, then divide ratio range is improved, but current consumption increases
Solution Approach 1:
The patent extracts and removes the problematic divide-by-one stages from the divider chain. Instead of using divide-by-one stages to extend the divide range, the invention disables downstream stages completely when they are not needed, thereby eliminating the additional current consumption associated with divide-by-one operation while maintaining the extended divide ratio range.
3Adaptability or versatility
If synchronous counter is used to change divide ratios, then adaptability is improved, but speed decreases and scalability is reduced
Solution Approach 1:
The patent segments the divider into multiple independent 2/3 divider stages that can be individually enabled or disabled. This segmentation allows each stage to operate independently at high speed, and by selectively enabling stages, the divider ratio can be changed programmatically without the speed penalties associated with synchronous counters, maintaining both adaptability and high operating speed.
Data Source
AI summary
A divider includes ⅔ divider stages that may be turned off without toggling to extend the divide range of the divider while also reducing the impact of spurs on the divider output, and preserving the timing margin to update the divide ratio glitchlessly. A ⅔ divider stage responds to an input enable signal being deasserted and a modulus input signal being asserted to remain in a disabled state in which the divider stage does not toggle by ensuring storage elements outputs in the divider stage remain constant. The divider further selects an update clock for the divide ratio of the divider utilizing an output from a most downstream stage that remains enabled.