Modified Decode Circuitry for Memory Corner Turn
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Solution Overview
Problem
Existing memory systems face inefficiencies in performing corner turn operations, which involve converting data between horizontal and vertical storage formats, often requiring complex decode circuitry and multiple instances of decode logic, leading to increased circuitry and computational overhead.
Innovation Solution
The implementation of modified decode circuitry that modifies addresses on a per-column select basis, allowing for efficient corner turn operations by reducing the need for complex decode circuitry and fewer instances of decode logic, enabling data to be stored and processed in both horizontal and vertical formats within the same memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex decode circuitry is used for corner turn operations, then data can be converted between horizontal and vertical storage formats, but circuitry requirements and computational overhead increase
Solution Approach 1:
The decode operation is segmented into row decode and column decode stages. The row decoder decodes the row address to select a specific row, while the column decoder decodes the column address to select specific columns. This segmentation allows the system to handle corner turn operations by independently controlling row and column selections, reducing the complexity of a single monolithic decoder.
Solution Approach 2:
The patent introduces an intermediary mechanism where the row decoder and column decoder work together through shared decode logic. The row decoder output serves as an intermediary signal that enables the column decoder to function, creating a staged decoding process that reduces overall circuit complexity compared to a single complex decoder.
2Adaptability or versatility
If multiple instances of decode logic are used for corner turn operations, then data format conversion is achieved, but circuitry requirements increase
Solution Approach 1:
The row decoder and column decoder are designed as universal decode units that can serve multiple functions. The same decoder circuitry is used for both row and column address decoding, allowing a single instance of decode logic to handle multiple addressing scenarios including corner turn operations, thereby reducing the total number of decode logic instances required.
Solution Approach 2:
The patent merges the decode logic for row and column addresses into a unified decoding architecture. By combining the functionality of multiple decode instances into a single integrated decode unit that handles both row and column addresses, the system reduces the quantity of decode logic while maintaining corner turn operation capability.
3Reliability
If traditional decode circuitry is used, then address decoding is performed, but processing efficiency is reduced
Solution Approach 1:
The row decoder performs preliminary decoding of the row address before the column decoder processes the column address. This preliminary action allows the system to pre-select the active row, enabling faster subsequent column decoding and data access. The staged approach ensures accurate address decoding while improving processing efficiency through optimized decode sequencing.
Data Source
AI summary
Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.