Modified Etch Stop Layers for Leakage-Safe Gate Vias
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Solution Overview
Problem
The formation of gate vias in semiconductor devices leads to unwanted coupling and leakage due to over-etching effects, causing the vias to get too close to source/drain contacts, which damages the trench sidewalls and increases complexity in IC manufacturing processes.
Innovation Solution
The implementation of modified etch stop layers surrounding the gate vias, which are selectively formed to prevent lateral over-etching during the formation of gate via trenches, using a plasma treatment to increase oxygen concentration in the sidewall surfaces, thereby acting as a buffer layer to protect the sidewalls from damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If deeper etching is used to form gate via trenches through multiple dielectric layers, then the gate vias can be formed at the required depth, but lateral over-etching occurs causing bowing effects and damage to trench sidewalls
Solution Approach 1:
The patent applies preliminary action by forming a protective layer on the sidewalls of the gate via trench before completing the etching process. This protective layer is deposited conformally on the trench sidewalls and then planarized, creating a buffer that prevents lateral over-etching and sidewall damage during the deeper etching required to penetrate multiple dielectric layers.
Solution Approach 2:
The patent implements beforehand cushioning by introducing a protective layer that acts as a cushion or buffer during the etching process. This layer absorbs the harmful effects of lateral over-etching, preventing direct damage to the trench sidewalls and maintaining manufacturing precision even when deeper etching is performed.
2Length of stationary object
If deeper etching is performed to form gate via trenches, then gate vias can reach the gate structure, but over-etching causes gate vias to get too close to source/drain contacts leading to leakage
Solution Approach 1:
The protective layer is formed preliminarily on the sidewalls before the complete etching process, establishing a buffer zone that controls the lateral etch front. This preliminary protection ensures that even with deeper etching, the gate vias maintain proper spacing from source/drain contacts, preventing leakage and improving device reliability.
3Ease of manufacture
If standard etch stop layers are used, then etching can proceed through dielectric layers, but they do not prevent lateral over-etching effects
Solution Approach 1:
The patent applies local quality by creating a protective layer with specific properties localized to the trench sidewall regions where protection is needed. Rather than modifying the entire etch stop layer uniformly, the protective layer is deposited conformally on the sidewalls and then planarized, providing localized protection exactly where lateral over-etching occurs, while maintaining ease of manufacture through standard deposition and planarization processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents lateral over-etching and subsequent leakage issues by maintaining the integrity of the gate via trenches, ensuring precise alignment and reducing manufacturing complexity while avoiding unnecessary layer formation costs.
Implementation Method 1
performing a plasma treatment on exposed side surfaces of the etch stop layer in the first trench, thereby forming a modification layer
Implementation Method 2
performing a plasma treatment to increase oxygen concentration in the sidewall surfaces
Data Source
AI summary
One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a source/drain (S/D) contact over an S/D feature; a gate structure over a channel region, where the channel region is adjacent the S/D feature; a first interlayer dielectric (ILD) layer over the gate structure and surrounding the S/D contact; an etch stop layer over the first ILD layer and the S/D contact, where the etch stop layer includes a first portion and a second portion, and the second portion is different from the first portion in chemical composition; a second ILD layer over the etch stop layer; and a gate via over the gate structure, where the gate via is surrounded by the second portion of the etch stop layer.