Modified Manchester Encoding for Variable-Rate Low-Power Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing interfaces for connecting a host processor with a peripheral device, such as a camera or sensor, require a dedicated clock lane, leading to increased circuit board space and power consumption, and traditional clock embedding schemes like 8b10b and Manchester encoding are inflexible and require PLLs, DLLs, or oversampling, which consume power and area, and do not allow for variable data rates.
Innovation Solution
A modified Manchester encoding scheme that embeds a clock signal into a data signal with fixed mid-bit transitions independent of link rate, allowing for variable link rates and eliminating the need for PLLs and long link training, using a compact CDR circuit to recover the clock signal without oversampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated clock lane is used to provide transmission clock for the receiver, then the receiver can sample data correctly, but the circuit board space and power consumption increase significantly
Solution Approach 1:
The patent merges the clock signal and data signal into a single data lane by embedding clock information within the data stream using modified Manchester encoding. This eliminates the need for a separate dedicated clock lane, reducing circuit board space while maintaining reliable data sampling through the embedded clock recovery mechanism.
Solution Approach 2:
The data lane is given multi-functionality by making it carry both data information and clock synchronization information simultaneously. The modified Manchester encoding scheme enables the single data lane to perform the dual role of transmitting data while also providing the clock reference needed for accurate sampling, eliminating the need for a separate clock lane.
2Reliability
If a dedicated clock lane is used to provide transmission clock, then the receiver can sample data correctly, but power consumption increases due to the extra lane and free running clock signal
Solution Approach 1:
The patent merges the clock signal and data signal into a single data lane by embedding clock information within the data stream using modified Manchester encoding. This eliminates the need for a separate dedicated clock lane, reducing circuit board space while maintaining reliable data sampling through the embedded clock recovery mechanism.
Solution Approach 2:
The modified Manchester encoding introduces periodic mid-bit transitions that occur at fixed time intervals independent of the link rate. These periodic transitions provide a stable clock reference for the receiver without requiring a free-running clock signal, thereby reducing power consumption while maintaining accurate data sampling.
3Adaptability or versatility
If traditional Manchester encoding is used to embed clock signal into data lane, then the clock is embedded, but the scheme is inflexible and requires PLLs, DLLs, or oversampling which consume power and area
Solution Approach 1:
The patent introduces dynamics by making the mid-bit transition timing fixed relative to boundary transitions rather than strictly mid-bit. This allows the encoding to adapt to variable link rates while maintaining a consistent time relationship between transitions, enabling flexible data rates without requiring complex PLL or DLL circuits for clock recovery.
Solution Approach 2:
The patent changes the encoding parameter from strict mid-bit transitions to fixed time-interval transitions after boundary transitions. This parameter change allows the system to operate at variable data rates while maintaining a predictable transition pattern that can be recovered without complex PLL, DLL, or oversampling circuits, thereby reducing device complexity and power consumption.
4Adaptability or versatility
If clock recovery from multiple data signals is performed, then clock information can be extracted, but jitter occurs in the recovered clock signal due to inter-lane skew and glitch signals
Solution Approach 1:
The patent extracts the clock information from a single data signal rather than attempting to recover it from multiple data signals. By embedding the clock reference within the single data stream using modified Manchester encoding, the system avoids the inter-lane skew and glitch signal problems that cause jitter when recovering clocks from multiple signals, thereby improving clock stability.
Data Source
AI summary
The present disclosure relates generally to an interface between a host processor device and a peripheral device, such as a camera or sensor, and, more particularly, to improving the generation of data signals with embedded clock information to be more rate-flexible and power efficient. Improved techniques are described herein to embed a clock signal into a data signal (e.g., to minimize the number of channels needed)—while allowing for a variable link rate and avoiding the need for a phase lock loop (PLL) and/or long link training times at the receiver, which can consume large amounts of power and on-chip area. In some embodiments, a modified Manchester encoding scheme, e.g., using a fixed delay for its mid-bit transitions (and wherein the delay is independent of link rate), is used to achieve the dual aims of rate flexibility and power efficiency for an improved data signal interface with embedded clock information.