Modified NAND Memory Architecture Charge Sharing Read
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Solution Overview
Problem
Traditional NAND flash memory architectures face limitations in increasing performance, including power consumption, speed, and memory density, necessitating alternative architectures and operation methods.
Innovation Solution
A modified NAND architecture where both ends of the NAND string are selectively coupled to the same bit line, allowing for programming and erasing similar to traditional NAND, but using charge sharing techniques for reading, similar to DRAM, which eliminates the need for a source connection and enables higher string lengths for improved data differentiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional NAND flash architecture is used, then programming and erasing can be accomplished, but read operations require separate source and bit lines which increases device complexity and limits performance
Solution Approach 1:
The patent merges the source and bit line connections by coupling both ends of the NAND string to the same bit line. This eliminates the need for separate source connections, simplifies the read operation, and reduces device complexity while maintaining programming and erasing capabilities.
Solution Approach 2:
The bit line is given multi-functionality by serving both as the source connection and the data read/write line. This universal connection approach allows the same bit line to handle both source potential application and data sensing, reducing the number of required connections.
2Quantity of substance
If longer NAND strings are used to increase memory density, then more cells can be stored, but conductance-based reading becomes less effective for data differentiation
Solution Approach 1:
The patent replaces conductance-based reading with charge-based reading. By using charge sharing techniques where the bit line capacitance shares charge with the floating gate of selected cells, the system achieves better data differentiation even in longer strings, enabling higher memory density without sacrificing measurement precision.
3Productivity
If conventional read operations are used, then data can be read from memory cells, but power consumption is higher and read speed is limited
Solution Approach 1:
The patent employs periodic voltage application to the bit line, where voltage is applied only during the specific time window when charge sharing occurs during read operations. This periodic action reduces overall power consumption compared to continuous voltage application in conventional reads, while maintaining fast read speeds through efficient charge sharing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, increases memory density, and facilitates faster read operations by leveraging capacitance instead of conductance, enabling higher string lengths and improved data value differentiation.
Implementation Method 1
reading of the memory cells in accordance with embodiments of the invention is accomplished using charge sharing techniques similar to read operations in a DRAM device
Implementation Method 2
During a read operation of a target memory cell of one of the sub-strings, the remaining sub-string serves as a storage node for a charge that is indicative of the data value of the target memory cell
Data Source
AI summary
Non-volatile memory devices utilizing a modified NAND architecture where both ends of the NAND string of memory cells are selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device.