Modified Source/Drain Structure for Lower GAA Parasitic Capacitance
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Solution Overview
Problem
Current methods for fabricating gate-all-around (GAA) transistors face challenges with high parasitic capacitance, leading to lower device speed and increased RC delays, which are not adequately addressed by existing design choices.
Innovation Solution
A method is introduced to modify the source/drain (S/D) features in GAA transistors by altering their morphology through surface treatment and selective etching, reducing parasitic capacitance without compromising device resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If separation distances between active device regions are reduced to meet design requirements of smaller technology nodes, then device density increases, but parasitic capacitance increases leading to lower device speed
Solution Approach 1:
The source/drain structure is segmented into multiple regions with different morphologies. The top portion is modified with surface treatment and selective etching to create a stepped or recessed structure, while the bottom portion maintains its original form. This segmentation allows different regions to serve different functions: the modified top region reduces parasitic capacitance with adjacent gates, while the bottom region maintains electrical connection and current flow.
Solution Approach 2:
The invention transitions from a planar source/drain structure to a three-dimensional stepped or recessed structure by modifying the top portion's morphology. This dimensional change creates vertical separation between the source/drain region and adjacent gate structures, reducing parasitic capacitance coupling in the vertical dimension while maintaining horizontal integration density.
2Object-generated harmful factors
If surface treatment and selective etching are applied to modify S/D feature morphology, then parasitic capacitance is reduced, but device resistance may be compromised
Solution Approach 1:
The surface treatment and selective etching are applied locally only to the top portion of the source/drain feature, not the entire structure. This localized modification reduces parasitic capacitance at the critical interface with adjacent gates while preserving the bulk electrical properties of the source/drain region. The bottom portion remains untreated to maintain optimal resistance characteristics.
Solution Approach 2:
Instead of modifying the entire source/drain structure, the invention applies partial action by treating only the top portion that is in proximity to adjacent gates. This selective approach removes just enough material to reduce parasitic capacitance to acceptable levels while leaving sufficient conductive material to maintain device resistance within specification limits.
Data Source
AI summary
A semiconductor structure includes semiconductor layers vertically stacked above a substrate, a gate structure wrapping around each of the semiconductor layers, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the semiconductor layers, and an S/D contact landing on a top surface of the S/D feature. In a cross-sectional view along a lengthwise direction of the semiconductor layers, a topmost point of the top surface of the S/D feature is above a top surface of a topmost one of the semiconductor layers, and a bottommost point of the top surface of the S/D feature is below the top surface of the topmost one of the semiconductor layers.