Modified Tri-State Circuit Layout for Lower ISI in Digital Links
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Solution Overview
Problem
Conventional digital circuits, such as PS converters and tri-state gates, suffer from inter-symbol interference (ISI) due to increased self-loading capacitance and reduced maximum output current, leading to errors in data transfer and reduced jitter tolerance.
Innovation Solution
A modified tri-state circuit design utilizing a pair of transistors (p-type and n-type MOS transistors) minimizes self-loading capacitance and optimizes charge/discharge times, reducing ISI and maintaining data integrity by synchronizing response times with clock signal edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional tri-state gates utilize multiple transistors in series configuration, then functional performance is achieved, but self-loading capacitance increases and maximum output current decreases
Solution Approach 1:
The patent divides the tri-state gate functionality into separate pull-up and pull-down networks, each using minimal transistors in parallel rather than series. This segmentation reduces the total number of series transistors from 3-8 to just 2, thereby reducing self-loading capacitance while maintaining functional performance through complementary CMOS architecture.
Solution Approach 2:
Instead of using series transistor configurations that increase capacitance, the patent inverts the approach by using parallel transistor configurations with complementary logic. The pull-up network uses p-type transistors in parallel while the pull-down network uses n-type transistors in parallel, reversing the conventional series approach and achieving lower capacitance.
2Reliability
If conventional tri-state gates utilize multiple transistors in series configuration, then functional performance is achieved, but maximum output current decreases
Solution Approach 1:
The patent segments the current path into separate pull-up and pull-down networks that operate independently. Each network uses parallel transistor configurations that provide multiple current paths, increasing the maximum output current compared to series configurations where current must flow through all transistors sequentially.
Solution Approach 2:
The patent inverts the conventional series configuration by using parallel transistor arrangements with complementary logic. This inversion allows maximum current to flow through parallel paths rather than being limited by the series combination of multiple transistor on-resistances, thereby increasing output current capability.
3Reliability
If charge/discharge time increases to accommodate intrinsic capacitance, then transistor sizing is adjusted, but response time becomes substantially larger than bit duration causing ISI
Solution Approach 1:
The patent segments the charging and discharging operations into separate, independent phases handled by complementary pull-up and pull-down networks. This allows each network to be optimized for its specific function with minimal transistors, reducing the total capacitance that needs to be charged or discharged and thereby reducing response time to within acceptable bit duration limits.
Solution Approach 2:
The patent changes the circuit parameters by using complementary CMOS architecture with minimal series transistors, which fundamentally alters the time constant (τ = RC) by reducing both the effective resistance (through parallel paths) and capacitance (through reduced transistor count). This parameter change ensures response time remains within bit duration requirements and prevents ISI.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes ISI, maintaining data integrity and increasing output data rates by reducing errors and jitter tolerance issues in digital circuits.
Implementation Method 1
Each transistor in the pull-up configuration or the pull-down configuration may have intrinsic capacitance, such as a self-loading capacitance. A maximum output current may be utilized to charge or discharge such intrinsic capacitance
Data Source
AI summary
A tri-state circuit that includes a control circuit coupled to a driver circuit. The driver circuit includes a first type of transistor connected in series with a second type of transistor. The control circuit receives an input data signal at an input data rate and a plurality of clock signals, and supplies a first signal and a second signal to the first type of transistor and the second type of transistor in response to the receipt of the input data signal. The control circuit further controls a tri-state switching operation of the first type of transistor and the second type of transistor such that the input data signal is selected and an output data signal is generated at an output data rate. The tri-state circuit is further utilized in other digital circuits, such as latch circuits, latch-based memory circuits or parallel-to-serial converter circuits to reduce inter symbol interference.