Modular 3D Semiconductor Package with Vertical and Horizontal Interconnects
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Solution Overview
Problem
Current semiconductor devices face challenges in minimizing the dedicated edge space required for interconnects between semiconductor die, which limits active die area and increases the overall package footprint, and struggle with heat dissipation and stress issues in stacked die configurations, particularly for power MOSFETs and integrated drivers.
Innovation Solution
The implementation of a modular 3D semiconductor package using inter-die interconnects with conductive layers formed on side surfaces of semiconductor die, allowing for direct contact and minimal separation, and the use of interconnect interposers with conductive vias and switching matrices to facilitate vertical and lateral routing, enabling efficient electrical interconnects and flexible package configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If bond wire interconnect is used between semiconductor die, then electrical connection is achieved, but dedicated edge space and separation distance are required, increasing package footprint
Solution Approach 1:
The patent transitions from planar wire bond interconnect to three-dimensional direct die-to-die contact, where contact pads on vertical side surfaces establish electrical connection without requiring lateral separation or edge space, thereby reducing package footprint while eliminating complex wire routing
2Area of moving object
If dedicated edge space is reserved for interconnect structures, then reliable electrical connection is achieved, but active die area is reduced
Solution Approach 1:
The patent moves interconnect contact from the two-dimensional die edge plane to the three-dimensional vertical side surface, allowing contact pads to be positioned on vertical faces rather than requiring lateral edge space, thereby maximizing active die area while maintaining reliable electrical connection
3Area of stationary object
If die stacking is used to minimize package footprint, then space efficiency is improved, but heat dissipation and stress issues worsen
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary between stacked die, providing thermal management capabilities and mechanical stress relief while enabling vertical stacking configuration, thereby addressing heat dissipation and stress issues associated with direct die-to-die stacking
4Ease of manufacture
If through silicon vias (TSVs) are used for inter-die interconnect, then vertical connection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the interconnect function from complex through-silicon via structures and implements it through simpler vertical side surface contact pads, eliminating the need for costly TSV fabrication processes while maintaining effective vertical electrical connection between die layers
Data Source
AI summary
A semiconductor device has a plurality of interconnected modular units to form a 3D semiconductor package. Each modular unit is implemented as a vertical component or a horizontal component. The modular units are interconnected through a vertical conduction path and lateral conduction path within the vertical component or horizontal component. The vertical component and horizontal component each have an interconnect interposer or semiconductor die. A first conductive via is formed vertically through the interconnect interposer. A second conductive via is formed laterally through the interconnect interposer. The interconnect interposer can be programmable. A plurality of protrusions and recesses are formed on the vertical component or horizontal component, and a plurality of recesses on the vertical component or horizontal component. The protrusions are inserted into the recesses to interlock the vertical component and horizontal component. The 3D semiconductor package can be formed with multiple tiers of vertical components and horizontal components.