Modular Accelerator Unit Active Interposer Multi-Die Support

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Solution Overview

Problem

Existing processing systems with silicon interposers are limited in their ability to support multiple dies and types of processor cores, restricting the flexibility and types of instructions and operations they can execute.

Innovation Solution

The implementation of an accelerator unit (AU) with a modular architecture, featuring active interposer dies (AIDs) that can concurrently support multiple compute dies of different types, including core complex dies (CCDs) and accelerated dies (ADs), through a scalable data fabric.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a silicon interposer is configured to support a set number of dies, then the processing device can execute a fixed set of instructions and operations, but the flexibility and adaptability of the processing device are limited

Engineering Contradiction:
ImproveflexibilityVSAvoidinterposer configuration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements an active interposer die that can dynamically support multiple types of compute dies (CCDs and ADs) through a reconfigurable data fabric. The interposer includes multiple types of interface circuits (first type for CCDs, second type for ADs) that can be selectively activated, allowing a single interposer design to serve multiple processing configurations and die types simultaneously.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of manufacture

If a silicon interposer supports only a certain type of die, then the manufacturing process is simplified, but the types of instructions and operations the processing device can execute are limited

Engineering Contradiction:
Improveinterposer manufacturing simplicityVSAvoiddie type support
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent segments the interposer functionality into distinct interface circuit types (first interface circuits for CCDs, second interface circuits for ADs) that are integrated into a single interposer die. This segmentation allows each interface type to be independently designed and configured while maintaining a unified interposer structure, enabling support for multiple die types without requiring separate interposer designs.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If the interposer supports multiple dies of different types, then the processing device can execute a wide range of applications, but the interposer must handle complex communication and data flow between different die types

Engineering Contradiction:
Improveapplication rangeVSAvoiddata fabric complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces an active interposer die as an intermediary between compute dies and memory stacks, containing a data fabric with multiple interface circuits that mediate communication between different die types. The interposer actively manages data flow routing, address translation, and protocol conversion between CCDs and ADs, simplifying the complexity by centralizing these functions in the interposer rather than requiring direct peer-to-peer communication between diverse dies.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250117352A1Acceleration unit with modular architecture
Publication Date: 2025.04.10 ADVANCED MICRO DEVICES INC
  • US20250117352A1 patent drawing
  • US20250117352A1 patent drawing
  • US20250117352A1 patent drawing

AI summary

A processing system includes one or more accelerator units (AUs) each having a modular architecture. To this end, each AU includes a connection circuitry and one or more memory stacks disposed on the connection circuitry. Further, each AU includes one or more interposer dies each disposed on the connection circuitry such that each interposer die of the one or more interposer dies is communicatively coupled to a corresponding memory stack of the memory stacks via the connection circuitry. Further, each interposer die of each AU includes circuitry configured to concurrently support two or more types of compute dies.