Modular Addition Instruction for Faster Homomorphic Encryption NTT
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Solution Overview
Problem
Homomorphic encryption (HE) operations in privacy-preserving machine learning (PPML) are computationally expensive due to bottlenecks in polynomial multiplication, particularly in modular addition and multiplication operations within the negacyclic number-theoretic transform (NTT), which hinder performance and efficiency.
Innovation Solution
Incorporation of specialized modular addition instructions, such as vpaddmoduq, that perform element-wise modular addition and subtraction operations to accelerate the forward and inverse NTT, reducing the computational burden in HE applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If homomorphic encryption operations are performed using conventional instructions, then data privacy is preserved, but computational expense and processing time increase significantly
Solution Approach 1:
The patent segments the modular addition operation into distinct computational stages: calculating the sum of two operands, determining whether the sum exceeds the modulus value, and conditionally subtracting the modulus. This segmentation allows each stage to be optimized independently, with the conditional subtraction only executed when necessary, thereby reducing overall computational overhead while maintaining encryption security
Solution Approach 2:
The patent changes the parameter representation by using dedicated modular addition instructions that natively support modular arithmetic operations. Instead of performing conventional addition followed by separate modulo operations, the system uses specialized instructions (such as vpaddmoduq) that perform modular addition in a single operation, changing the computational parameter from multi-step to single-step execution
2Ease of manufacture
If conventional addition and multiplication instructions are used for NTT operations, then implementation simplicity is maintained, but the number of instructions required increases
Solution Approach 1:
The patent creates universal modular addition instructions that can handle various NTT operation requirements through a single instruction type. The vpaddmoduq instruction serves multiple functions: it performs the modular addition required in forward NTT, in inverse NTT, and in polynomial multiplication operations, eliminating the need for different instruction sequences for different NTT variants
Solution Approach 2:
The patent merges multiple conventional instructions into a single modular addition instruction. Instead of requiring separate instructions for addition, comparison, and conditional subtraction, the system combines these operations into one atomic instruction that performs modular addition in a single execution cycle, thereby reducing the total instruction count while maintaining implementation simplicity
3Measurement precision
If modular addition operations are performed using multiple conventional instructions, then operational accuracy is maintained, but processing speed decreases
Solution Approach 1:
The patent performs preliminary calculation of the sum of two operands before the conditional subtraction step. The vpaddmoduq instruction first computes the full sum of the two input values, then determines in a single operation whether this sum exceeds the modulus. This preliminary action ensures accuracy is maintained while minimizing the number of subsequent operations required
Data Source
AI summary
One embodiment provides a processor comprising first circuitry to decode an instruction into a decoded instruction, the instruction to indicate a first source operand, a second source operand and a third operand, and second circuitry including a processing resource to execute the decoded instruction. Responsive to the decoded instruction, the processing resource is to output a result of a modular addition operation based on a data element of first source operand data plus a data element of second source operand data modulo a data element of third operand data, provided that the data elements of the first operand data and second operand data are less than the data element of the third operand data.