Modular Analog MAC Units With Asynchronous Charge Transfer
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Solution Overview
Problem
Existing multiplier-accumulators in machine learning applications suffer from high power consumption due to synchronous clocked operations and require complex gate structures, especially for large multiply-accumulate operations, and lack a unified architecture for multiplier-accumulator, bias, and analog-to-digital converter unit elements.
Innovation Solution
A scalable asynchronous multiplier-accumulator architecture with a unified structure for MAC, Bias, and ADC unit elements, utilizing a shared differential charge transfer bus and binary weighted charge transfer capacitors, along with a successive approximation register controller for efficient power management and reduced common mode imbalances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If synchronous clocked stages are used for multiplier operations, then operation speed is improved, but power dissipation increases due to displacement currents
Solution Approach 1:
The patent employs periodic action by using asynchronous charge transfer driven by input signal changes rather than continuous clocking. The multiplier-accumulator operates in discrete phases triggered by data transitions, eliminating continuous clock signals and associated displacement currents while maintaining computational speed through event-driven operation.
Solution Approach 2:
The patent replaces the mechanical clocking system with an asynchronous charge transfer mechanism. Instead of using clock edges to synchronize operations, the system uses direct charge transfer from multiplication results to accumulation nodes, eliminating the need for clocked stages and reducing power dissipation from displacement currents.
2Productivity
If large n×n multiplier is implemented for machine learning, then computational capability is improved, but gate complexity increases as n2
Solution Approach 1:
The patent segments the large multiplier-accumulator into multiple smaller MAC units that can operate in parallel. Each MAC unit handles a portion of the computational task, and the results are accumulated through shared charge transfer lines. This segmentation reduces the complexity of individual units while maintaining the overall computational capability for large n×n operations.
Solution Approach 2:
The patent implements multi-functionality by using shared charge transfer lines and common accumulation nodes that serve multiple MAC units simultaneously. The same charge transfer infrastructure is used for both multiplication and accumulation operations, as well as for bias input and ADC functions, reducing the total gate complexity while maintaining high computational capability.
3Adaptability or versatility
If multiple separate architectures are used for MAC, Bias, and ADC unit elements, then functional flexibility is improved, but overall system complexity increases
Solution Approach 1:
The patent merges the MAC unit, Bias unit, and ADC unit into a unified architecture sharing common charge transfer lines and accumulation nodes. The same differential charge transfer bus is used for all three functions, eliminating the need for separate architectures while maintaining functional flexibility through configurable unit elements.
Solution Approach 2:
The patent implements universality by designing a common unit element structure that can function as MAC UE, Bias UE, or ADC UE depending on configuration. The same basic architecture with differential charge transfer lines and binary weighted capacitors serves all three functions, reducing system complexity while maintaining adaptability through software or control-based configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution minimizes power consumption by eliminating displacement currents and common mode imbalances, providing a flexible and efficient architecture for machine learning operations with reduced noise and offset errors.
Implementation Method 1
each NAND gate having a positive output coupled through a binary weighted positive charge transfer capacitor to a positive charge transfer line and a negative output coupled through a binary weighted negative charge transfer capacitor to a negative charge transfer line
Data Source
AI summary
An analog machine learning architecture uses modular analog multiplier-accumulator (AMAC) elements of fixed size to form a machine learning (ML) system with increasing feature map size. A single 3×3×64 AMAC array is arranged to provide a three layer ML architecture with first layer 3×3×64, second layer 3×3×128, and third layer 3×3×256 using arrangements of single 3×3×64 AMACs arranged in parallel, where the bias of each AMAC is separately established in a unique interval of time.