Modular Arithmetic Unit with Internal Data Handler for Secure Cryptography

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Solution Overview

Problem

Existing modular arithmetic units in RSA and ECC algorithms are inefficient due to high memory access requirements, which affects the performance of these cryptographic systems.

Innovation Solution

A modular arithmetic unit design that includes a data handler with parallel registers to store and shift operands, reducing memory accesses by internally storing operation results and frequently used data, and optimizing hardware usage to decrease power consumption and exposure to external attacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If modular arithmetic units frequently access memory for operations, then data can be retrieved, but operating speed decreases and power consumption increases

Engineering Contradiction:
Improveoperating speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent implements preliminary action by pre-loading frequently used data (modulus M, operands A and B) into internal registers before cryptographic operations begin. The data handler loads these values into dedicated registers in advance, so they are immediately available during modular exponentiation operations without requiring memory access during the actual computation, thereby improving speed and reducing power consumption.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary data handler component that acts as a buffer between memory and the modular arithmetic unit. This data handler includes registers that store frequently accessed data, mediating the interaction between slow memory and fast arithmetic operations. By placing this intermediary layer, the system reduces direct memory accesses while maintaining data availability, thus improving operating speed and reducing power consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If modular arithmetic units access memory frequently, then data is available, but security exposure to external attacks increases

Engineering Contradiction:
ImprovesecurityVSAvoidexposure to external attacks
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies the taking out principle by extracting frequently used cryptographic data (modulus M, operands A and B) from external memory and placing them into internal registers of the modular arithmetic unit. This extraction removes sensitive data from the external memory interface, reducing the attack surface. By keeping data internally during operations, the system minimizes exposure to external attacks while maintaining data availability for cryptographic computations.

Inventive Principle:
Principle #2Taking out (Extraction)

3Device complexity

If modular arithmetic units use more memory accesses, then data can be stored externally, but device complexity increases

Engineering Contradiction:
Improvehardware structureVSAvoidoperation time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent applies merging by combining the data handling functionality with the modular arithmetic unit. The data handler is integrated directly into the arithmetic unit structure, sharing the same hardware resources and control logic. This integration eliminates the need for separate memory management hardware and reduces overall device complexity while enabling fast internal data access that reduces operation time.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9098381B2Modular arithmatic unit and secure system including the same
Publication Date: 2015.08.04 SAMSUNG ELECTRONICS CO LTD
  • US9098381B2 patent drawing
  • US9098381B2 patent drawing
  • US9098381B2 patent drawing

AI summary

A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.