Modular Barrett Reduction Circuit with Cache Memory

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Solution Overview

Problem

Existing modular reduction methods in cryptography, such as those used in RSA or El Gamal, face high latency and require large circuitry due to inefficient pre-computation and calculation processes, particularly in handling large numbers.

Innovation Solution

A modular reduction device that combines a cache memory with a binary division circuit to avoid repetitive pre-calculations, utilizing a cache to store recent values of pre-computed results and a binary division circuit to calculate them when needed, thereby reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If generalized Barrett method is used for modular reduction, then calculation speed is improved, but latency increases due to pre-computation of μ

Engineering Contradiction:
Improvecalculation speedVSAvoidlatency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The invention pre-calculates and stores the μ values in a lookup table during an initialization phase, so that during actual modular reduction operations, these pre-computed values can be directly retrieved without adding latency to the critical path of the calculation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent prepares and stores the necessary pre-computation results (μ values) in advance in a dedicated memory structure, cushioning against the potential latency issue by having these values ready before they are needed in the modular reduction process

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Productivity

If Montgomery method is used for modular reduction, then calculation efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvecalculation efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The invention extracts the complex pre-computation step (calculating μ) out of the critical path of the modular reduction operation and performs it separately during initialization, allowing the main reduction logic to remain simple and efficient without the overhead of repeated complex calculations

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs the complex pre-computation of μ values in advance during system initialization or first use, storing them for later retrieval, thereby separating the complex setup phase from the simpler operational phase of modular reduction

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If Euclidean division is used for modular reduction, then algorithm generality is maintained, but calculation latency increases for large numbers

Engineering Contradiction:
Improvealgorithm generalityVSAvoidcalculation latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The invention pre-calculates the μ parameter that depends only on the divisor q, storing it for reuse across multiple modular reduction operations with the same modulus, thereby converting a repeated expensive operation into a single pre-computation followed by fast lookups

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent transforms the modular reduction problem by introducing a pre-computed parameter μ that changes the calculation approach from direct Euclidean division to a multiplication-based method that leverages the pre-stored value, effectively changing the computational parameters to achieve better performance

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3451316B1Modular reduction device
Publication Date: 2022.04.13 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
  • EP3451316B1 patent drawingFigure 1
  • EP3451316B1 patent drawingFigure 2
  • EP3451316B1 patent drawingFigure 3

AI summary

The present invention relates to a modular reduction device, particularly for elliptic curve cryptography. The device comprises a modular Barrett reduction circuit (210) and a cache memory (220) in which the results of certain pre-calculations are stored. When the result is not present in the cache memory, a binary division circuit (230) performs the pre-calculation and stores the result in the cache memory.