Modular Bonding Apparatus for High-Density Wafer Stacking
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Solution Overview
Problem
The complexity of wafer logistics and reduced productivity in semiconductor assembly processes due to the stacking of multiple layers of wafers in Cu—SiO2 hybrid bonding, where the bonding force is weak, leading to issues like chip fly during stacking, transfer, or annealing processes.
Innovation Solution
A modular bonding apparatus with multiple load ports, transferers, bonding devices, cleaners, and pretreatment devices that include pre-annealing ovens to perform primary annealing before secondary annealing, ensuring strong bonding and preventing chip detachment, while allowing for efficient handling and stacking of wafers of varying sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple layers of wafers are stacked to increase integration density, then the semiconductor package height is reduced, but the bonding strength becomes insufficient leading to chip detachment
Solution Approach 1:
The patent applies preliminary action by performing pre-annealing on wafers before stacking and bonding them. The pre-annealing process activates the SiO2 layers and prepares the copper bumps, creating stronger bonds that can withstand the stress of multiple-layer stacking. This preliminary treatment ensures that even when 16 or more layers are stacked, the bonding strength remains sufficient to prevent chip detachment.
Solution Approach 2:
The patent changes physical parameters by controlling the annealing temperature and duration to activate the SiO2 layers and copper bumps. By optimizing these parameters, the bonding strength is enhanced significantly, allowing high-density stacking without chip fly issues. The parameter changes transform the material properties to achieve both high stacking density and strong bonding.
2Volume of moving object
If Cu-SiO2 hybrid bonding is used to eliminate protruding bumps, then the package height is reduced, but the wafer logistics flow becomes complicated
Solution Approach 1:
The patent segments the bonding process into distinct stages: pre-annealing, stacking, and secondary annealing. By dividing the complex Cu-SiO2 hybrid bonding process into manageable segments, the wafer logistics flow becomes more organized and controllable. Each segment can be optimized independently, reducing overall process complexity while maintaining the compact package height advantage.
Solution Approach 2:
The patent introduces pre-annealing as an intermediary step between wafer preparation and final bonding. This intermediary process activates the bonding surfaces in advance, simplifying the subsequent stacking and bonding operations. The pre-annealing acts as a mediator that reduces the complexity of handling multiple layers by ensuring all wafers are properly prepared before assembly.
3Device complexity
If standard bonding process is used without pre-annealing, then the process is simpler, but chip detachment occurs during stacking and transfer
Solution Approach 1:
The patent applies preliminary action by performing pre-annealing on wafers before stacking and bonding them. The pre-annealing process activates the SiO2 layers and prepares the copper bumps, creating stronger bonds that can withstand the stress of multiple-layer stacking. This preliminary treatment ensures that even when 16 or more layers are stacked, the bonding strength remains sufficient to prevent chip detachment.
Solution Approach 2:
The patent uses pre-annealing as a cushioning measure to prevent future bonding failures. By treating the wafers in advance, the system compensates for the potential weakness that would otherwise lead to chip fly during stacking and transfer operations. This beforehand cushioning ensures bonding reliability without requiring complex real-time monitoring or correction mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances productivity by preventing chip detachment during subsequent processes, allowing for efficient stacking and annealing of up to 16 layers of wafers, reducing delays, and improving overall semiconductor packaging efficiency.
Implementation Method 1
a pre-annealing oven configured to pre-anneal the plurality of bonded substrate wafers
Implementation Method 2
copper-copper (Cu—Cu) secondary bonding is performed by using thermal expansion of a copper element filled in a via hole by applying heat at a high temperature through an annealing process
Implementation Method 3
primary bonding is performed between silicon dioxide (SiO2) layers by using van der Waals force
Data Source
AI summary
Provided is a bonding apparatus including a first wafer supplier including a plurality of load ports configured to store wafers having different sizes, the wafers including a plurality of substrate wafers and a plurality of die supply wafers, a first transferer adjacent to the first wafer supplier and configured to transfer the wafers, a first bonding device and a second bonding device facing the first wafer supplier, and configured to receive the wafers from the first wafer supplier and perform bonding, and a first cleaner comprising a plurality of cleaning areas, each of which is configured to receive the plurality of substrate wafers and the plurality of die supply wafers by the first transferer, and clean the plurality of substrate wafers and the plurality of die supply wafers.