Modular Integrated Capacitor Architecture with Leakage Detection
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Solution Overview
Problem
Existing integrated capacitor architectures for voltage down converters, particularly in sub-micrometric technologies, face challenges due to high area occupation on silicon and reliability issues with oxide layers, leading to inefficiencies and increased costs.
Innovation Solution
The proposed architecture splits an integrated capacitor into modular capacitors that can be selectively activated, using a capacitive block with PMOS switches and a verify and enable circuit to detect leakage currents and deactivate faulty modules, minimizing area occupation and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If an integrated capacitor is implemented using conventional architectures in sub-micrometric technologies, then the capacitor can provide the necessary capacitance value, but the silicon area occupation becomes excessively large
Solution Approach 1:
The integrated capacitor is divided into multiple modular capacitor units that can be independently activated or deactivated. Each module contains capacitor elements connected through switching transistors, allowing selective activation based on operational requirements. This segmentation enables the system to achieve the necessary total capacitance while occupying minimal silicon area by only activating the required number of modules.
2Ease of manufacture
If conventional oxide layers are used in sub-micrometric technologies, then the capacitor can be fabricated using standard processes, but reliability issues arise due to oxide faults and leakage currents
Solution Approach 1:
The patent implements quality control at the individual module level rather than requiring perfect quality across the entire capacitor structure. Each modular unit can be independently tested and characterized, allowing faulty modules to be identified and deactivated while maintaining operation of healthy modules. This local quality approach maintains compatibility with standard fabrication processes while compensating for oxide layer defects through selective module deactivation.
Solution Approach 2:
The system includes mechanisms to detect and discard (deactivate) faulty capacitor modules that exhibit leakage currents or other defects. The verify and enable circuit tests each module and disables only those that fail quality thresholds, allowing the capacitor to continue operating with the remaining healthy modules. This approach recovers functionality by excluding only the defective portions while maintaining overall system operation.
3Quantity of substance
If all capacitor modules are activated to achieve the required capacitance, then the necessary capacitance value is obtained, but the complexity of managing and verifying each module increases
Solution Approach 1:
Each capacitor module is equipped with self-test and self-verification capabilities through integrated switching transistors and verification circuits. The modules automatically indicate their operational status through current measurements during a verification phase, allowing the system to identify which modules are functional without requiring complex external testing equipment. This self-service approach simplifies the overall management complexity by distributing the verification function across individual modules.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces silicon area usage by 60% while maintaining performance, as demonstrated in simulations, and allows for efficient integration in channel modulation converters by effectively managing leakage currents and oxide faults.
Implementation Method 1
a capacitive block (11) inserted between a first and a second voltage reference and comprising a plurality of elementary capacitive modules
Implementation Method 2
An enable block (12) is inserted between said first voltage reference and said capacitive block (11) and comprises a plurality of switches connected to said elementary capacitive modules
Implementation Method 3
A verify and enable circuit (13) is connected to said first voltage reference and to the input of said first end of said elementary capacitive modules and to the output of said control terminals of said switches of said enable block (12), said verify and enable circuit (13) detecting the presence of a current value in each elementary capacitive module
Data Source
AI summary
An architecture for implementing an integrated capacity includes a capacitive block inserted between first and second voltage reference. The block is formed The block is formed from elementary capacitive modules. An enable block is inserted between the first voltage reference and the capacitive block and includes switches connected to the elementary capacitive modules and driven on their control terminals by control signals. Each switch of the enable block is inserted between the first voltage reference and a first end of a corresponding elementary capacitive module. A verify and enable circuit is connected to the first voltage reference, as well as at the input of the first end of the elementary capacitive modules and at the output of the control terminals of the switches of the enable block. The verify and enable circuit detects the presence of a current value in each of the elementary capacitive modules and, if said current is detected, disables that elementary capacitive module of the capacitive block using the corresponding switch of the enable block.