Modular Chip Integration via Segmented Voltage Islands
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Solution Overview
Problem
Modular chip fabrication faces compatibility issues due to changes in chip feature sizes and power requirements, limiting the versatility of current design technology, as 'old' and 'new' technologies often become incompatible.
Innovation Solution
The integration of chips and chip macros on a single carrier platform with segmented power and ground inputs and outputs to form voltage islands, using conductive vias and a wiring layer to facilitate the integration of heterogeneous chip technologies, allowing for the reuse of pre-designed components and supporting new chip designs with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chip feature sizes are reduced to increase functionality and reduce power consumption, then the number of functionalities and power efficiency improve, but compatibility between old and new technologies deteriorates
Solution Approach 1:
The patent segments the power supply system into multiple voltage islands, each capable of providing different voltage levels to different chip components. This allows older components requiring higher voltages to coexist with newer components operating at lower voltages, resolving the compatibility issue while maintaining the benefits of scaled-down feature sizes.
Solution Approach 2:
The patent implements local quality by providing different voltage levels to different spatial regions (voltage islands) on the chip. Each voltage island is tailored to the specific power requirements of the components within it, allowing heterogeneous integration of components with different power needs without requiring uniform voltage across the entire chip.
2Adaptability or versatility
If all components are redesigned into the latest node to maintain compatibility, then compatibility is improved, but power consumption increases and versatility is reduced
Solution Approach 1:
By segmenting the power supply into multiple voltage islands, the patent enables older, less power-efficient components to operate at their required voltage levels while newer components operate at lower, more efficient voltages. This selective voltage provision maintains compatibility without forcing all components to adopt the latest power-consuming node.
Solution Approach 2:
The patent introduces dynamic voltage control through switches that can selectively connect different voltage islands to power sources. This dynamic capability allows the system to adapt power distribution to the actual operational needs of different components, maintaining compatibility while optimizing power consumption based on which components are active.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of diverse chip technologies, reducing power requirements, latency, and increasing bandwidth, while allowing for easier integration of advanced technologies with existing ones, thereby enhancing the versatility and efficiency of chip design.
Implementation Method 1
The carrier platform can comprise a plurality of conductive vias extending therethrough; and a wiring layer thereon in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands
Data Source
AI summary
Modular chip integration and operation techniques are provided. In one aspect, a method of integrating chips, chip macros or at least one chip in combination with at least one chip macro is provided. The method comprises the following steps. The chips, chip macros or at least one chip in combination with at least one chip macro are assembled on a single carrier platform. One or more signal inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. One or more power and ground inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. The power and ground inputs and outputs to one or more of the chips, chip macros or at least one chip in combination with at least one chip macro are segmented from the power and ground inputs and outputs to at least one other of the chips, chip macros or at least one chip in combination with at least one chip macro so as to form a plurality of voltage islands.