Modular Chiplet Fabric With Active Interposer for Low-Power Composability
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Solution Overview
Problem
The use of chiplets in integrated circuit products faces challenges such as limited system composability, high costs associated with custom-designed passive interposers, and significant power consumption in die-to-die communication, making it impractical for high-performance applications.
Innovation Solution
The modular chiplet system employs an active semiconductor substrate with a network-on-chip and a fabric device that includes a built-in network-on-chip, 3D chiplet interfaces, and a library of rotationally symmetrical chiplets. This system reduces lateral communication distances, enables efficient packet routing, and allows for the creation of various system permutations using a small set of chiplets and fabric devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If custom-designed passive interposers are used for chiplet-based products, then system performance is improved, but design and manufacturing cost increases
Solution Approach 1:
The patent implements a universal active interposer design that can serve multiple chiplet configurations and system requirements. The reconfigurable fabric allows the same interposer hardware to support different chiplet arrangements, communication patterns, and system architectures, eliminating the need for custom-designed passive interposers for each application while maintaining high system performance.
Solution Approach 2:
The interposer incorporates reconfigurable fabric that can dynamically adapt its configuration based on the specific chiplet arrangement and communication requirements. This dynamic reconfiguration capability allows the interposer to optimize performance for different scenarios without requiring custom design, reducing both design complexity and manufacturing cost while maintaining reliability.
2Area of moving object
If long side-to-side communication distances are used in 2D/2.5D chiplet approach, then chiplet interface area is reduced, but power consumption increases
Solution Approach 1:
The patent transitions from 2D/2.5D lateral communication to 3D vertical communication through stacked chiplet architectures. By moving communication paths to the vertical dimension via through-silicon vias and three-dimensional integration, the system achieves shorter effective communication distances and reduced power consumption while maintaining compact interface areas.
Solution Approach 2:
The active interposer serves as an intermediary that facilitates efficient communication between chiplets. It provides buffered interfaces, signal regeneration, and intelligent routing that reduce the power consumption of long communication paths while maintaining compact interface areas through optimized signal transmission.
3Ease of manufacture
If consolidation of designs from different vendors is performed, then development cost is reduced, but system composability is limited
Solution Approach 1:
The patent segments the system into standardized, modular chiplet components with well-defined interfaces and a reconfigurable fabric. This segmentation allows designs from different vendors to be integrated through standardized interfaces while the reconfigurable fabric provides the flexibility to compose diverse system configurations, maintaining both cost efficiency and system composability.
Solution Approach 2:
The reconfigurable fabric provides universal support for multiple chiplet types, configurations, and communication patterns. This universality enables consolidation of designs from different vendors into a common platform while maintaining the ability to compose diverse system configurations, preserving both cost benefits and system adaptability.
4Area of moving object
If advanced process nodes with high transistor density are used, then chiplet size is reduced, but communication interface area overhead increases
Solution Approach 1:
The patent merges the communication interface functionality directly into the active interposer fabric rather than requiring separate interface circuits on each chiplet. This consolidation eliminates redundant interface overhead on small chiplets while the active interposer provides centralized, efficient communication management for high-density advanced process node chiplets.
Data Source
AI summary
A modular chiplet system enables numerous unique systems to be created from a small set of chiplets and a fabric device. The modular chiplet system includes an active semiconductor substrate with a built-in network-on-chip, chiplet interfaces for connecting to stacked chiplets, power delivery networks, clocking, system management, and general-purpose I/O. A set of mechanically and electrically interchangeable rotationally symmetrical chiplets can be connected to the active semiconductor interposer, at one site of an array of N×M sites. The rotational symmetry enables I/O chiplets to be placed at any side of the active semiconductor substrate. The modular chiplet system includes a shared memory architecture that allows the chiplets to communicate with each other using memory mapped addressing and read/write transactions that are routed by the network-on-chip. The network-on-chip also enables communication between resources on or accessible via the active semiconductor substrate.