Modular Chiplet Integration Package for Low-Warpage Assembly
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Solution Overview
Problem
Multi-die integration packages face significant risks of failure due to increased size, particularly in machine learning applications exceeding 5,000 mm2, leading to reduced manufacturing yield and increased costs.
Innovation Solution
A modularized construction approach using an elevated fan-out bridge with minimal redistributed layers and sub-modules, allowing pre-fabrication and testing of individual components before integration, and employing materials like glass interposers and solder interconnects to mitigate warpage and stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multi-die integration packages grow in size to meet machine learning application requirements, then the module area can exceed 5,000 mm2 to accommodate complex functions, but the risk for failure of IC die bond to die stack substrate increases significantly
Solution Approach 1:
The patent divides the large multi-die integration package into multiple smaller sub-modules, each with its own die stack substrate. This segmentation reduces the area of each individual substrate, thereby reducing the risk of die bond failure in each segment while still achieving the required total module area of over 5,000 mm2 through assembly of multiple segments.
2Adaptability or versatility
If multi-die integration packages grow in size, then more complex functions can be integrated, but the gross die per reconstituted wafer is reduced to single digit numbers
Solution Approach 1:
By segmenting the integration package into smaller sub-modules, the patent enables higher density arrangement of multiple sub-modules on a single wafer. This increases the gross die per reconstituted wafer from single digits to potentially dozens or hundreds of sub-modules per wafer, thereby improving productivity while maintaining the capability to integrate complex functions through modular assembly.
Solution Approach 2:
The patent employs standardized sub-module designs with universal interfaces and interconnection protocols. This universality allows different sub-modules to be mixed and matched in various configurations to achieve different complex functions, enabling high adaptability while maintaining high productivity through standardized manufacturing processes.
3Adaptability or versatility
If complex multi-die structures are integrated, then more functionality is achieved, but manufacturing yield is significantly reduced
Solution Approach 1:
The patent segments the complex multi-die structure into smaller, simpler sub-modules that are easier to manufacture with high yield. Each sub-module can be manufactured, tested, and validated independently, and then assembled into the complete functional system. This approach maintains high functionality while significantly improving manufacturing yield compared to attempting to manufacture complex structures in a single integrated process.
Solution Approach 2:
The patent implements preliminary fabrication and testing of individual sub-modules before final assembly. This preliminary action allows for early detection and correction of manufacturing defects, ensuring that only high-yield sub-modules proceed to final assembly. This staged approach maintains high functionality while improving overall manufacturing yield by filtering out defects early in the process.
Data Source
AI summary
Modularized construction of a structure is used for a multi-die integration package. Segregation of complex devices into substructures (sub-modules) are tested and verified as functional before final reconstitution into the multi-die integration package. The thermal coefficient of sub-modules can be fine-tuned for low chip module warpage. The sub-modules can be made with a glass interposer tuned with a certain coefficient of thermal expansion (CTE) and modulus to provide favorable warpage performance. Solder interconnects at high stress locations may be used to further reduce via and polyimide (PI) stresses. A minimal redistributed layer (RDL) comprising conductive metal patterns with a plurality of metal contacts thereon is formed on a polyimide (PI) or glass carrier and electrically interconnects the sub-modules together.