Modular Command Structure for Memory Systems
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Solution Overview
Problem
In multi-device semiconductor memory systems, existing command structures often lead to processing delays and low input/output utilization due to serial interconnection configurations, where one memory device must complete commands before others can process, restricting the use of multiple memory banks and reducing system performance.
Innovation Solution
A modular command structure is introduced, comprising a device identifier with an address for memory devices and a bank address for memory banks, along with a command identifier representing operations, allowing for separatable commands that can be processed independently by each memory device, enabling concurrent operations across multiple devices and banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory devices are serially interconnected in a chain configuration, then device complexity is reduced and ease of manufacture is improved, but processing speed and input/output utilization deteriorate due to command delays
Solution Approach 1:
The command structure is segmented into distinct fields including device identifier, bank address, and command identifier. This segmentation allows each memory device in the serial chain to independently parse and process commands intended for it, eliminating the need to wait for previous devices to complete processing, thus improving processing speed while maintaining serial interconnection simplicity
Solution Approach 2:
The controller acts as an intermediary that translates processor requests into modular commands with specific device identifiers and bank addresses. This intermediary function enables precise routing of commands to specific memory devices and banks within the serial chain, allowing concurrent operations and improving overall system productivity without changing the physical serial connection topology
2Device complexity
If a common bus is used to connect memory devices to the controller, then device complexity is reduced, but input/output utilization deteriorates because only one device can be asserted at a time
Solution Approach 1:
The command structure incorporates local quality by including specific device identifiers and bank addresses that allow each memory device to independently identify and process commands intended for it. This enables multiple devices to be actively processed simultaneously over the common bus, improving input/output utilization while maintaining the simplicity of common bus connectivity
3Ease of operation
If series-connected memory devices are used, then ease of operation is improved, but processing speed deteriorates because command transmission is halted at each device
Solution Approach 1:
The command is segmented with clear device identifier and bank address fields that enable each memory device in the series connection to independently determine whether the command is intended for it. This allows commands to be rapidly forwarded through devices without processing delays, improving processing speed while maintaining the ease of operation associated with series connections
Data Source
AI summary
A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.