Modular Compilation Flows for Programmable Logic Devices
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Solution Overview
Problem
The long compilation time for programmable logic devices, such as high-capacity FPGAs, is computationally intensive, resource-intensive, and cost-intensive due to their fine-grained nature, leading to increased development costs and reduced adoption.
Innovation Solution
Implementing modular routing configurations and pre-compiling possible routing configurations to reduce compile time, allowing routing to be performed via the programmable logic device's routing network without excess area or performance overhead, and utilizing network-on-chips for improved memory transport and spatial decoupling of logic resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fine-grained programmable logic devices are used to compile register transfer level designs, then the device can be programmed to perform a wide variety of operations, but the compilation time becomes computationally intensive and resource intensive
Solution Approach 1:
The patent pre-compiles routing configurations and stores them in a library before the actual compilation process. When a design needs to be compiled, the pre-compiled routing configurations are retrieved and applied, significantly reducing the compilation time while maintaining the fine-grained programmability of the device
2Adaptability or versatility
If routing is implemented using soft-routing with post-compile configurable multiplexers and look-up tables, then routing flexibility is improved, but more storage, logic, configuration time, and compile time are consumed
Solution Approach 1:
The patent creates pre-compiled copies of routing configurations and stores them in a library. Instead of generating routing configurations from scratch during compilation, the system copies pre-validated routing configurations from the library and applies them to the design, reducing both storage requirements and compilation complexity
Solution Approach 2:
Routing configurations are pre-computed and stored in a library before the actual compilation process. This preliminary action eliminates the need to perform complex routing computations during compilation, reducing device complexity while maintaining routing flexibility
3Manufacturing precision
If design is decomposed down into millions of primitives for fine-grained compilation, then the design can be implemented with high precision, but the compilation process becomes computationally intensive and cost intensive
Solution Approach 1:
The patent pre-compiles routing configurations for fine-grained primitives and stores them in a library. When compiling a design decomposed into millions of primitives, the system retrieves pre-compiled routing configurations from the library rather than computing them from scratch, maintaining precise decomposition while dramatically improving compilation efficiency
Solution Approach 2:
Pre-compiled routing configurations for individual primitives are copied from the library and applied to the decomposed design elements, avoiding redundant computation and reducing the overall compilation burden while maintaining the precision of fine-grained decomposition
Data Source
AI summary
Systems or methods of the present disclosure may provide an electronic device that includes memory storing instructions; and a processor, that when executing the instructions, is to receive a design for a programmable fabric of an integrated circuit device. The instructions are also to cause the processor to cause compilation of the design into a configuration during a compilation window. The instructions further are to cause the processor to determine at least some routing for the configuration outside of the compilation window.