Hardware Accelerator Modular Division Inversion
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Solution Overview
Problem
Cryptographic operations, particularly in public-key cryptography systems like RSA and elliptic curve cryptography, face computational bottlenecks due to the high cost of modular division and inversion operations, which consume significant processing resources and require large memory storage for precomputed values.
Innovation Solution
The implementation of a hardware accelerator device and instruction set architecture that efficiently performs modular division and inversion using techniques such as Montgomery reduction and extended binary Euclidean algorithms, eliminating the need for precomputed modular inverses and reducing memory usage by utilizing multiple registers for different multiples of the modulus and eliminating branching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional modular division and inversion operations are used in cryptographic algorithms, then computational correctness is ensured, but processing resources are significantly consumed and operation speed is reduced
Solution Approach 1:
The patent segments the modular division operation into multiple stages: computing quotient and remainder through bit-by-bit processing, then separately handling the modular reduction. This segmentation allows the system to avoid expensive traditional modular division while maintaining correctness through systematic breakdown of the computation into manageable steps that can be optimized.
Solution Approach 2:
The patent replaces the traditional mechanical modular division algorithm with a substitution based on modular multiplication and conditional addition. Instead of performing direct modular division which is computationally intensive, the system uses modular multiplication by precomputed values and conditional additions, which are significantly faster and more efficient in hardware implementation.
2Productivity
If precomputed modular inverses are stored for fast inversion operations, then inversion speed is improved, but memory storage requirements increase significantly
Solution Approach 1:
The patent performs preliminary computation of modular inverses on-demand using the extended Euclidean algorithm or other inversion methods, then caches only the essential intermediate results needed for future operations. This approach provides fast inversion capability without requiring storage of all possible precomputed inverses, thus balancing speed with memory efficiency.
Solution Approach 2:
The system implements self-service modular inversion by computing inverses dynamically when needed rather than relying on precomputed tables. The inversion computation is integrated into the cryptographic operation flow, allowing the system to generate required inverses on-demand using efficient algorithms, eliminating the need for large precomputed inverse tables.
3Adaptability or versatility
If a unified hardware accelerator is designed to support both RSA and ECC operations, then device versatility is improved, but device complexity increases
Solution Approach 1:
The patent designs a unified cryptographic accelerator that implements a common computational core capable of performing both RSA and ECC operations. The core uses generic modular arithmetic operations (multiplication, addition, conditional operations) that are algorithm-agnostic, allowing the same hardware structure to support multiple cryptographic algorithms through configuration rather than dedicated hardware for each algorithm.
Solution Approach 2:
The system achieves versatility through parameter changes rather than structural changes. By modifying operational parameters such as the modulus, key size, and operation type (encryption, decryption, signing, verification), the same hardware accelerator can efficiently execute different cryptographic algorithms including RSA and ECC, eliminating the need for separate dedicated hardware for each algorithm.
Data Source
AI summary
Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as modular division and modular inversion, using shared platforms, including hardware accelerator engines.