Modular Circuit Emulation Clock Synchronization
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Solution Overview
Problem
Existing circuit emulation systems face limitations in supporting certain I/O peripherals, flexibility in capacity, and run speeds, often requiring operation at frequencies less than 1-3 MHz, which is slower than actual ASIC designs.
Innovation Solution
A modular and scalable circuit emulation system utilizing multiple programmable boards with FPGAs, a broadcast bus, and a system backplane with a switching matrix, allowing for flexible configuration and expansion, including serialization and deserialization modules, clock buffers, and phase correction to enhance interconnectivity and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing emulation systems are used, then circuit emulation functionality is provided, but run speeds are limited to frequencies less than 1-3 MHz
Solution Approach 1:
The emulation system is divided into multiple independent emulation boards that can be stacked and configured independently. Each board contains its own FPGA resources and can operate semi-autonomously, allowing the system to achieve higher overall speeds by distributing the emulation workload across multiple segments rather than being limited by a single board's clock frequency.
Solution Approach 2:
The system transitions from a single-board two-dimensional layout to a multi-board three-dimensional stacked configuration. This vertical stacking approach allows multiple emulation resources to be combined while maintaining signal integrity through controlled impedance backplane connections, effectively increasing capacity and speed without sacrificing reliability.
2Adaptability or versatility
If existing emulation systems are used, then basic emulation capability is provided, but support for certain I/O peripherals is inadequate
Solution Approach 1:
The emulation boards are designed with universal I/O capabilities that can support multiple types of peripherals through configurable FPGA logic. The standardized backplane and board architecture allow the same hardware platform to adapt to different peripheral requirements by loading appropriate bitstreams, eliminating the need for dedicated hardware for each peripheral type.
Solution Approach 2:
The system employs dynamically reconfigurable FPGA logic that can be programmed at runtime to support different I/O peripheral protocols and interfaces. This dynamic adaptability allows the emulation system to switch between different peripheral support modes without physical reconfiguration, maintaining versatility while managing complexity through software control.
3Adaptability or versatility
If existing emulation systems are used, then fixed capacity is provided, but flexibility in terms of capacity is limited
Solution Approach 1:
The emulation system is segmented into multiple identical or heterogeneous boards that can be stacked in various configurations. Each board represents a discrete capacity unit that can be independently configured and removed, allowing the system capacity to be flexibly adjusted by simply adding or removing boards from the stack without requiring complex reconfiguration of the entire system.
Solution Approach 2:
The system is designed to support partial configurations where not all boards need to be populated or activated. Users can configure the system with exactly the number of boards required for a given emulation task, leaving spare boards available for future expansion or different applications, thus providing capacity flexibility without requiring full system utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system provides enhanced support for I/O peripherals, increased capacity, and improved run speeds, enabling the emulation of complex ASIC designs with frequencies exceeding 10 MHz, thus addressing the limitations of existing systems.
Implementation Method 1
The clock buffer 170 may include a phase locked loop 172 that receives the input clock signal 164 and generates the synchronized clock signal 176 based on the input clock signal
Implementation Method 2
Each emulation board 100, 101, . . . may include a serialization module 180 that converts parallel data signals to a serialized data stream
Implementation Method 3
Another emulation board 101 may include a deserialization module 190 that converts the serialized data stream back into parallel data signals
Implementation Method 4
The system backplane 106 may include a switching matrix that selectively couples the emulation boards to one another
Data Source
AI summary
A modular circuit emulation system includes a global clock generator that generates a plurality of clock signals. A plurality of emulation boards each include at least one programmable circuit and a clock buffer. The clock buffer generates at least one synchronized clock signal for clocking the programmable circuit or circuits, based on at least one of the plurality of global clock signals.