Modular Exponentiation Engine for Federated Learning
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Solution Overview
Problem
Federated learning faces challenges in computing performance due to the need for large integer modular multiplication operations, particularly with algorithms like RSA, Paillier, and DH, which require extensive processing resources and hinder data collaboration across organizations.
Innovation Solution
A processing device and method that includes modular exponentiation engines, pre-processing, montgomerization, confusion calculation, and montgomery reduction modules, allowing flexible execution of different operator modes to optimize modular exponentiation operations, transforming them into multiple modular multiplication operations for improved efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional modular exponentiation algorithms (RSA, Paillier, DH) are used in federated learning, then privacy security is ensured through encryption, but computing performance deteriorates due to extensive large integer modular multiplication operations
Solution Approach 1:
The patent segments the modular exponentiation operation into multiple modular multiplication operations. By breaking down the complex exponentiation task into simpler multiplication steps, the system can process each segment in parallel, thereby improving computing performance while maintaining the security properties of the original encryption algorithms.
Solution Approach 2:
The patent merges multiple modular multiplication operations into a unified parallel processing framework. By combining several computation steps that can be executed simultaneously, the system achieves better resource utilization and faster overall processing speed without compromising the cryptographic security requirements.
2Adaptability or versatility
If multiple encryption algorithms are supported for different operator modes in federated learning, then adaptability is improved, but device complexity increases due to needing separate processing circuits for each algorithm
Solution Approach 1:
The patent designs a universal processing device that can handle multiple encryption algorithms (RSA, Paillier, DH) and various operator modes through a single unified circuit architecture. This multi-functional design eliminates the need for separate dedicated circuits for each algorithm, thereby reducing device complexity while maintaining broad adaptability.
Solution Approach 2:
The patent implements a dynamic configuration capability that allows the processing device to adapt its operation mode based on the specific algorithm and operator mode requirements. This dynamic adaptability enables a single circuit to efficiently handle different cryptographic operations without requiring static dedicated hardware for each case.
Data Source
AI summary
A processing device for federated learning, including: a modular exponentiation module including at least one modular exponentiation engine; a pre-processing module for providing operations corresponding to a plurality of operator modes; a montgomerization module for providing montgomerization operations; a confusion calculation module for providing modular multiplication operations in montgomery space; a montgomery reduction module for providing montgomery reduction operations; and a controller for determining, according to an input operator mode, whether to enable at least two modules out of the pre-processing module, the montgomerization module, the confusion calculation module, and the montgomery reduction module, so as for cooperatively performing the input operator mode together with the modular exponentiation module.