Modular Frequency Divider for Programmable Integer Clock Division
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Solution Overview
Problem
Existing frequency dividers are limited in their ability to perform integer division for divisors beyond a predetermined upper limit, particularly in generating secondary signals with precise timing for transitions, which is challenging for frequencies that are not integer multiples of the primary signal.
Innovation Solution
A modular frequency divider circuit comprising a series of identical modules, each with input, output, and control ports, allowing for programmable frequency division by factors of one, two, or three, and interconnected to achieve division by any integer up to a predetermined upper limit, using a controller to configure the module division control inputs for specific divisor values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a frequency divider is designed to handle only a predetermined upper limit of divisors, then the device complexity is reduced, but the adaptability is limited
Solution Approach 1:
The frequency divider is segmented into multiple identical modules, each capable of dividing by 1, 2, or 3. By connecting N modules in series, the system can achieve division by any integer from 1 to 2^N, providing extensive adaptability without requiring a completely different circuit for each divisor value.
Solution Approach 2:
Each module is designed with multi-functionality, capable of performing three different division operations (by 1, 2, or 3) based on control signals. This universal module design allows the same hardware to serve multiple purposes, increasing the overall adaptability of the frequency divider system.
2Ease of operation
If the frequency divider uses a fixed circuit design for specific divisors, then the manufacturing precision is improved, but the ease of operation deteriorates
Solution Approach 1:
The frequency divider transitions from a static fixed circuit to a dynamic reconfigurable system. Control signals can dynamically adjust the division factor of each module, allowing the system to adapt to different divisor requirements without physical reconfiguration or redesign.
Solution Approach 2:
Instead of designing unique circuits for each divisor value, the invention uses multiple copies of the same modular unit. This standardized copying approach simplifies manufacturing while maintaining programmability through control signals that configure each copied module according to the desired division factor.
3Manufacturing precision
If the module performs division by three, then the range of achievable divisors is expanded, but the timing precision for transitions may be affected
Solution Approach 1:
The control signal configuration allows different modules in the series to have different division factors (1, 2, or 3) based on local requirements. This local quality approach enables precise control of transition timing in critical modules while using higher division factors in other modules to expand the overall range of achievable divisors.
Data Source
AI summary
A frequency divider includes a circuit that receives an input clock signal having a period T on an input port thereof and generates an output clock signal on an output port thereof having a period MT in response to a control signal specifying M is disclosed. Here, M is a positive integer and all transitions between logical one and logical zero in the output clock signal occur at integer multiples of T. In one embodiment, the circuit includes a module string having characterized by N identical modules connected in series to form a string of modules. Each module is configured such that when the clock signal having period T is input to the first module, the output clock signal having a period of MT is output from the last module, where M can have any value between one and a maximum number that depends on N.