Modular Gated Multiplier Circuitry for Power-Efficient Multiplication
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Solution Overview
Problem
Conventional multiplier designs experience glitching issues due to inefficient layout designs, particularly when handling smaller numbers, which affects power management and efficiency in machine learning applications.
Innovation Solution
The implementation of a modular low power gated multiplier structure using 8×8 bit integer multipliers constructed from multiple 4×4 multipliers and gating elements, which reduces power consumption by selectively activating only necessary parts of the circuitry based on input values, utilizing product logic, summation logic, and latching logic to generate and compress partial products.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional multipliers are designed to handle the largest number range (0 to 255 or -255 to 255), then they can process all possible input values, but they cause glitching problems and waste power when handling smaller numbers
Solution Approach 1:
The patent divides the multiplier circuit into multiple segments or modules, each capable of handling specific input ranges. The circuit uses selection logic to activate only the necessary segment based on the input values, preventing unnecessary switching activity in inactive segments and thereby reducing power consumption and glitching while maintaining full input range capability.
2Adaptability or versatility
If multipliers use 8-bit logic built to handle numbers within range 0 to 255, then they can process full byte-range inputs, but they exhibit glitching problems due to complicated and inefficient layout designs
Solution Approach 1:
The patent segments the 8-bit multiplier into smaller modular units with standardized interfaces. This segmentation allows for more systematic and efficient layout design, reducing signal path complexity and interconnections that cause glitching, while preserving the ability to process full 8-bit input ranges.
Solution Approach 2:
The patent introduces dynamic control mechanisms that adaptively enable or disable circuit paths based on input values. This dynamic behavior optimizes the active circuit topology for each operation, reducing unnecessary switching and glitching while maintaining full byte-range processing capability.
Data Source
AI summary
Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.