Modular Imaging Detector ASIC Segmentation for Channel Yield
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Solution Overview
Problem
The existing imaging detector technologies require multiple optimized ASICs for different detector configurations, leading to manufacturing inefficiencies and high costs due to the need for specific channel counts, which limits the applicability and increases waste from improperly functioning channels.
Innovation Solution
A single modular ASIC is developed that can be divided into fully functional reduced channel ASICs, allowing a single fabrication to produce various channel counts, optimizing cost and size across different detector configurations, and enabling the reuse of properly functioning channels from a larger ASIC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple different optimized ASICs are developed for different detector configurations, then each ASIC is optimized for specific channel counts, but manufacturing inefficiencies and costs increase
Solution Approach 1:
The patent implements a universal ASIC architecture that can function with multiple channel counts (64, 128, 256, 512 channels) through a single design. The ASIC includes a bank of channel processing units that can be selectively activated, allowing the same hardware to serve different detector configurations without requiring separate optimized designs for each channel count.
Solution Approach 2:
The ASIC is segmented into multiple independent processing channels that can be selectively enabled or disabled. Each channel processing unit is modular, allowing the ASIC to be configured for different numbers of active channels based on the specific detector array requirements, thereby improving manufacturing efficiency while maintaining optimization.
2Manufacturing precision
If multiple different optimized ASICs are developed for different detector configurations, then each ASIC is optimized for specific channel counts, but development time and cost increase
Solution Approach 1:
The patent implements a universal ASIC architecture that can function with multiple channel counts (64, 128, 256, 512 channels) through a single design. The ASIC includes a bank of channel processing units that can be selectively activated, allowing the same hardware to serve different detector configurations without requiring separate optimized designs for each channel count.
Solution Approach 2:
The ASIC design allows parameter changes in channel count through selective activation of processing units rather than requiring different physical designs. The same ASIC can be reconfigured for different channel counts by changing which processing units are active, eliminating the need for time-consuming separate development cycles for each configuration.
3Adaptability or versatility
If higher end ASICs with more channels are used for all imaging system configurations, then all systems can use the same ASIC, but size and cost become prohibitive for lower end systems
Solution Approach 1:
The patent implements a dynamic ASIC configuration where the number of active processing channels can be adjusted based on the specific imaging system requirements. Lower-end systems can activate only the necessary number of channels (e.g., 64 or 128), while higher-end systems can utilize all available channels (e.g., 512), allowing the same physical ASIC to adapt to different complexity requirements without being prohibitively large or expensive for any single application.
4Reliability
If ASICs with improperly functioning channels are discarded, then quality is maintained, but overall yield decreases
Solution Approach 1:
The patent implements a strategy where ASICs with partially defective channels are not discarded but rather reconfigured to activate only the functional channels. The modular channel processing architecture allows the system to identify and activate only the working channels, recovering value from ASICs that would otherwise be rejected and improving overall manufacturing yield while maintaining quality standards.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing inefficiencies and costs by allowing a single ASIC to serve multiple detector configurations, improving yield by reusing functional channels and minimizing waste, while maintaining performance across different pixel counts.
Implementation Method 1
A detector array subtends an angular arc opposite the examination region from the x-ray tube. The detector array detects radiation that traverses the examination region and generates a signal indicative thereof.
Data Source
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Figure 4~5
AI summary
An imaging system detector array (112) includes a detector tile (116). The detector tile includes a photosensor array (202), including a plurality of photosensor pixels (204). The detector tile further includes a scintillator array (212) optically coupled to the photosensor array. The detector tile further includes an electronics layer or ASIC on a substrate (214) that is electrically coupled to the photosensor array. The electronics layer includes a plurality of individual and divisible processing regions (302). Each processing region including a predetermined number of channels corresponding to a sub-set of the plurality of photosensor pixels. The processing regions are in electrical communication with each other. Each processing region includes its own electrical reference and bias circuitry (802, 804).