Modular Interconnect Frame Layout for Simpler BEOL Routing
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Solution Overview
Problem
The complexity and cost of manufacturing semiconductor devices increase due to the numerous steps involved in their integration, leading to inefficiencies in the fabrication process.
Innovation Solution
A semiconductor device design featuring an interconnect part with a lower redistribution layer, an upper redistribution layer, and an interconnect frame, along with a passivation structure, which simplifies the back-end-of-line (BEOL) routing and reduces fabrication costs and time through a modular design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional semiconductor device integration methods are used, then device functionality is achieved, but manufacturing complexity and fabrication cost increase
Solution Approach 1:
The semiconductor device is divided into distinct functional modules: a device substrate containing transistor structures, and a separate interconnect part containing redistribution layers and interconnect frames. This segmentation allows each module to be manufactured and processed independently, reducing overall manufacturing complexity while maintaining full device functionality.
Solution Approach 2:
The interconnect part is extracted as a separate component from the device substrate. By removing the interconnect structures from the traditional monolithic integration approach, the patent enables independent processing of the device substrate, simplifying the manufacturing workflow and reducing fabrication steps.
2Productivity
If more integration steps are implemented, then device functionality is enhanced, but fabrication time and cost increase
Solution Approach 1:
The interconnect part is prepared in advance as a separate component with pre-formed redistribution layers and interconnect frames. This preliminary preparation allows the interconnect part to be ready for attachment to the device substrate, eliminating the need for time-consuming in-situ interconnect formation steps during final device assembly.
Solution Approach 2:
By segmenting the device into independently manufacturable modules (device substrate and interconnect part), each can be fabricated simultaneously or in parallel using optimized processes, thereby reducing total fabrication time while enhancing device functionality.
Data Source
AI summary
The present disclosure provides a semiconductor device with an interconnect part and a method for preparing the semiconductor device. The semiconductor device comprises a device substrate and an interconnect part disposed over the device substrate. The interconnect part includes a lower redistribution layer electrically connected to the backside contact, and an upper redistribution layer disposed over the lower redistribution layer. The interconnect part also includes an interconnect frame disposed between and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect part further includes a passivation structure surrounding the interconnect frame.