Modular Interconnection Units for Low Profile 3D Fan-Out Packages
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Solution Overview
Problem
Current semiconductor packaging methods, particularly the formation of redistribution layers (RDLs), face challenges such as high fabrication costs, limited mechanical strength, reduced design flexibility, and structural limitations due to the need for temporary bonding with high-temperature resistant materials, which complicates the formation of electrical interconnections in 3D fan-out semiconductor packages.
Innovation Solution
The use of prefabricated modular interconnection units with vertical interconnects that reduce the number of RDLs required, providing structural support and flexibility by being disposed around the semiconductor die, thereby simplifying the manufacturing process and enhancing design capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional redistribution layers (RDLs) are used for electrical interconnection in 3D fan-out semiconductor packages, then electrical connectivity is achieved, but fabrication costs increase and mechanical strength decreases
Solution Approach 1:
The patent segments the RDL structure into multiple thinner layers (first RDL, second RDL, third RDL) distributed across different substrates rather than using a single thick RDL. This segmentation reduces the mechanical stress concentration, improves overall mechanical strength, and allows each layer to be formed using standard low-cost fabrication processes on separate substrates that are later stacked together.
Solution Approach 2:
The patent implements a nested structure where multiple RDL layers are stacked within each other across different substrates (first substrate, second substrate, third substrate). Each RDL layer is nested within the vertical stack, with the first RDL on the first substrate, second RDL on the second substrate, and third RDL on the third substrate, creating a compact nested arrangement that improves mechanical strength while maintaining electrical connectivity.
2Reliability
If multiple RDLs are formed over front and back surfaces of semiconductor die, then electrical interconnection is achieved, but temporary bonding with high-temperature resistant materials is required, complicating the manufacturing process
Solution Approach 1:
The patent segments the electrical interconnection function across multiple separate substrates with individual RDL layers, rather than forming all RDLs on a single substrate requiring high-temperature bonding. Each substrate can be processed independently at lower temperatures, and the substrates are later assembled together, simplifying the manufacturing process while achieving the same electrical interconnection function.
Solution Approach 2:
The patent transitions from a planar 2D arrangement of RDLs on a single substrate to a 3D vertical stack across multiple substrates. This dimensional change allows electrical interconnection to be achieved through vertical stacking of thinner RDL layers on separate substrates, eliminating the need for high-temperature bonding processes required for thick planar RDLs.
3Ease of manufacture
If thin stacks of RDLs are used, then fabrication cost is reduced, but structural limitations and reduced design flexibility occur
Solution Approach 1:
The patent segments the RDL structure into multiple thin layers across different substrates, which reduces the cost of each individual RDL layer while the modular stacked architecture provides enhanced design flexibility. Each substrate can be independently designed and optimized for specific functions, allowing greater adaptability in the overall system design.
Solution Approach 2:
The patent creates a universal modular stacked substrate architecture where multiple thin RDL layers on different substrates can serve various functions (signal routing, power distribution, grounding) simultaneously. This multi-functional modular design provides both cost efficiency and design flexibility, as the same basic stacked structure can be adapted for different application requirements.
4Adaptability or versatility
If vertical interconnection units with modular interconnects are used, then design flexibility and mechanical strength are improved, but the structure becomes more complex
Solution Approach 1:
The patent segments the vertical interconnection into modular units distributed across multiple substrates, where each substrate contains a portion of the interconnect structure. This segmentation provides design flexibility by allowing independent optimization of each module while the overall structural complexity is managed through standardized interfac e designs between modules.
Solution Approach 2:
The patent combines multiple thin RDL layers on separate substrates into a unified vertical interconnection structure. This merging approach achieves the desired design flexibility and mechanical strength by integrating the functions of multiple layers into a compact stacked architecture, while the modular nature of the combination keeps the structural complexity manageable through standardized interfaces.
Data Source
AI summary
A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect structure disposed within the vias.