Modular Input Output Ports for Clock Alignment
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Solution Overview
Problem
Conventional ASIC design is labor-intensive and power-consuming due to the need for manual intervention in clock tree synthesis and timing closure, which is susceptible to process, voltage, and temperature variations, and requires strategic placement of buffers to minimize clock skew.
Innovation Solution
The implementation of modular input and output ports with converters, buffers, routers, and Quality of Service/Fault Tolerant blocks to manage data streams, optimize throughput, and maintain Quality of Service, allowing for efficient clock signal distribution and reduced power consumption across ASIC chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If buffers are strategically placed to minimize clock skew, then clock alignment is improved, but device complexity and power consumption increase
Solution Approach 1:
The system uses self-calibrating phase-locked loops at each IP block that automatically adjust their own clock phase without external intervention. The PLLs monitor their local clock skew and autonomously tune delay elements to achieve alignment, eliminating the need for manual buffer placement and reducing design complexity.
Solution Approach 2:
The invention dynamically adjusts clock signal parameters (phase and delay) using controllable delay elements within each PLL. By changing the delay parameter locally at each receiver, the system achieves clock alignment adaptively rather than through fixed buffer placement, reducing both complexity and power consumption.
2Manufacturing precision
If buffers are added along the clock signal path, then clock skew is reduced, but power consumption increases
Solution Approach 1:
Each IP block's PLL independently calibrates its own clock phase by monitoring local skew conditions and adjusting internal delay elements. This self-service approach eliminates the need for power-hungry buffer insertion while maintaining precise clock skew control through localized, adaptive phase adjustment.
Solution Approach 2:
The invention extracts the clock alignment function from the global clock distribution network and places it locally within each IP block's PLL. By taking out the phase adjustment capability from the central buffer insertion approach and distributing it to individual blocks, the system reduces overall power consumption while maintaining skew control.
3Manufacturing precision
If manual intervention is used for clock tree synthesis, then timing closure is achieved, but productivity decreases
Solution Approach 1:
The system implements automated, self-calibrating PLLs that perform timing closure autonomously without manual intervention. Each PLL independently measures its clock skew and adjusts its phase accordingly, replacing the labor-intensive manual clock tree synthesis process with automated self-adjusting circuitry that maintains timing closure while dramatically improving productivity.
Solution Approach 2:
The invention incorporates feedback mechanisms where each PLL monitors its local clock signal quality and skew conditions, then uses this feedback to automatically adjust its phase and delay parameters. This closed-loop feedback system achieves timing closure automatically, eliminating the need for iterative manual intervention and accelerating the design process.
Data Source
AI summary
Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.