Modular Memory Access Bank With Arbitration Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital systems with shared Ram memory banks cannot handle simultaneous access by multiple peripherals and are not scalable to accommodate varying numbers of peripherals without redesigning the entire system.
Innovation Solution
A digital device with a central unit and a bank of modules, each with a priority value, a multiplexer, and arbitration cells, allowing multiple peripherals to write/read data simultaneously while maintaining priority and scalability through modular design and plug & play functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock signal is used to manage memory access as in prior art systems, then timing control is simplified, but simultaneous access by multiple peripherals cannot be achieved
Solution Approach 1:
The system segments the memory access control into multiple independent modules, each with its own clock signal and arbitration cell. This allows each peripheral to operate independently with its own timing, enabling simultaneous access while maintaining individual timing control through modular segmentation of the access control function.
2Device complexity
If a fixed system architecture is designed for a specific number of peripherals, then the system structure is simplified, but the system cannot accommodate varying numbers of peripherals without redesign
Solution Approach 1:
The system employs dynamic module addition/removal capability where peripherals can be connected or disconnected from the modular bank without affecting the core system architecture. The arbitration cell automatically adapts to the current number of active peripherals, enabling the system to dynamically adjust its configuration and maintain functionality with varying peripheral counts.
Solution Approach 2:
The modular bank of modules is designed with universal interfaces and standardized arbitration mechanisms that can accommodate any number of peripherals. Each module follows the same structure and communication protocol, allowing the system to universally handle different configurations of peripherals without requiring architecture redesign.
3Ease of operation
If priority-based arbitration is implemented for multiple peripherals, then access order is controlled, but the system complexity increases
Solution Approach 1:
Each peripheral module contains its own arbitration cell that autonomously determines access priority based on predefined criteria. The arbitration cells independently evaluate their own readiness and compete for memory access without requiring centralized arbitration logic, enabling priority control while distributing the complexity across multiple self-managing units.
Data Source
AI summary
A device and method for writing/reading a piece of data in/from a memory register shared by a plurality of peripherals, each peripheral having a peripheral clock signal, when two or more of the plurality of peripherals need to write/read such piece of data at the same time, the digital device including a central unit having the memory register and a bank of SL modules in signal communication with the central unit, the bank of SL modules being designed to write/read the piece of data. The bank of SL modules comprises a plurality of writing/reading modules whose priority value ranges between maximum and minimum priority values, each module being connected to a respective peripheral, the central unit includes a multiplexer in signal communication on the one hand with the plurality of writing/reading modules, and on the other hand with the memory register, each module comprises an arbitration cell, such that the first module is identified by the maximum priority value (Prmax′) and the other N−1 modules are identified by decreasing priority values, the central unit operating at a predetermined main clock frequency to write/read the piece of data in the memory register.