Modular Memory Cell With Parallel Read Circuit
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Solution Overview
Problem
Conventional memory cell structures require complex state machines for sequential decoding and have high bit-flip immunity issues during read operations, with inefficient data reloading processes.
Innovation Solution
A modular memory cell design incorporating a floating gate transistor, latch circuit, and integrated read circuit with enable signals that allow parallel read operations, reducing the need for state machines and enhancing data reliability through local bit-line buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional memory cell structures are used with sequential decoding, then the control logic can be simplified, but the read operation speed decreases and complexity increases due to state machine requirements
Solution Approach 1:
The memory cell is divided into two independent floating gate transistors (first and second FG transistors) that can be read in parallel through separate select transistor pairs. This segmentation allows simultaneous read operations without requiring sequential state machine control, thus improving read speed while keeping control logic simple.
Solution Approach 2:
The patent uses periodic enable signals (first and second enable signals) to control the read operations of the two floating gate transistors. By alternating or simultaneously activating these enable signals, the system achieves parallel periodic read operations without complex sequential control, resolving the contradiction between speed and complexity.
2Reliability
If conventional read operations are performed without local buffering, then the circuit area can be reduced, but bit-flip immunity deteriorates during read operations
Solution Approach 1:
The patent merges the read circuit functionality directly into each memory cell by integrating local buffering circuits at the latch nodes. This combination of memory storage and read buffering functions within the same cell structure improves bit-flip immunity through local signal reinforcement without requiring separate peripheral buffering circuits, thus maintaining compact area.
Solution Approach 2:
Each memory cell performs its own read buffering operation through integrated local circuits that sense and hold the read data at the latch nodes. This self-service approach provides bit-flip immunity at the cell level without relying on external peripheral circuits, achieving high reliability within minimal area.
3Speed
If parallel read operations are implemented without modular cell design, then the read speed improves, but the device complexity increases due to inter-cell interference and control requirements
Solution Approach 1:
The memory array is segmented into independent modular cells, each containing its own floating gate transistors, select transistors, and latch circuits. This segmentation isolates each cell's read operation, enabling parallel reads without inter-cell interference while maintaining simple control signals that can be uniformly applied across all cells.
Solution Approach 2:
The modular cell design uses universal control signals (word lines, select lines, enable signals) that serve multiple functions across different cells. The same control signal structure enables both individual and parallel read operations, simplifying the control architecture while achieving high read speed through parallel operation of identical modular units.
Data Source
AI summary
A memory cell for use within a memory array includes a memory circuit and a read circuit. The memory circuit includes a non-volatile memory element (for example, a floating gate transistor) coupled to an RS flip flop. The RS flip flop is configured with a p-channel transistor coupled to receive a first enable signal and an n-channel transistor coupled to receive a second enable signal. The assertion of the enable signals is offset in time to control operations for forcing latch nodes to a specific voltage and enabling latching operation. The read circuit includes latch circuit coupled to outputs of the RS flip flop and operable as a sense amplifier circuit. The memory and read circuits are fabricated within a rectangular circuit area. Many such rectangular circuit area may be positioned adjacent to each other in a row or column of the memory array.