Modular Memory Die Layout for Scalable IC Capacity
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Solution Overview
Problem
Current memory vendors require different die designs and manufacturing processes for various memory sizes, leading to increased time, cost, and complexity in producing memory modules with different capacities, as well as multiple attachment steps for integrated circuit devices.
Innovation Solution
A modular memory building block architecture where a single type of wafer with tiled memory modules can be used to create different memory capacities by singulating dies of varying sizes, allowing for scalable memory solutions across different integrated circuit devices with different memory needs, using the same underlying memory technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If different die designs and manufacturing processes are used for different memory sizes, then manufacturing optimization for each memory capacity is improved, but device complexity and resource requirements increase
Solution Approach 1:
The patent implements a universal memory module design that can be used across multiple memory capacities (8GB, 16GB, 32GB, etc.). Instead of designing unique memory modules for each capacity, the same standardized module is manufactured and then different numbers of modules are attached to achieve different total capacities. This reduces design complexity while maintaining manufacturing optimization through standardized processes.
Solution Approach 2:
The memory system is divided into discrete, standardized memory modules that can be independently manufactured and then combined in different quantities. Each memory module is a self-contained unit with standardized interfaces, allowing the system to achieve different total capacities by attaching different numbers of identical modules rather than designing custom memory structures for each capacity.
2Productivity
If different die designs are used for different memory capacities, then manufacturing efficiency for each capacity is improved, but loss of time and resources increases
Solution Approach 1:
The memory modules are pre-manufactured as standardized components with all necessary design and fabrication completed in advance. This allows the final assembly process to simply involve attaching the pre-made modules to the memory device, eliminating the need for time-consuming custom design and implementation for each memory capacity variant.
Solution Approach 2:
A single standardized memory module design serves multiple purposes across different memory capacity requirements. The same module design is manufactured in volume, improving manufacturing efficiency through economies of scale, while the modular approach allows flexible configuration for different total capacities without additional design time.
3Adaptability or versatility
If multiple attachment steps are used for different memory capacities, then customization for different capacities is improved, but device complexity and resource requirements increase
Solution Approach 1:
The memory system uses discrete, standardized memory modules that can be attached in different quantities to achieve different total capacities. The segmentation into identical modular units simplifies the attachment process compared to custom designs, as the same attachment procedure is repeated for each module rather than implementing complex custom integration for each capacity level.
Solution Approach 2:
The system achieves different memory capacities by changing the quantity parameter (number of modules attached) rather than changing the design parameters of the modules themselves. This allows customization for different capacities while maintaining a simple, standardized attachment process for identical modules.
Data Source
AI summary
In embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. The memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. The first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (TSVs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).