Large-Integer Modular Multiplication With Single Correction Addition
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Solution Overview
Problem
Existing hardware implementations for modular addition and multiplication of large integers, particularly in elliptic curve cryptography, are slow and computationally intensive, especially for operands exceeding 255 bits, due to the need for multiple modular reductions and complex correction terms.
Innovation Solution
A method and system that utilize a binary adder followed by a single modular correction term to perform modular addition of multiple operands, allowing parallel execution of binary additions and reducing the need for individual modular reductions, utilizing a binary adder, multiplexers, and selection units to achieve faster execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional multiplication algorithms (schoolbook or Karatsuba) are used, then implementation simplicity is maintained, but computation time becomes prohibitively slow for large integers
Solution Approach 1:
The patent segments the multiplication problem by representing integers in a radix representation system where numbers are divided into chunks of log2(N) bits. This segmentation allows the use of Fast Fourier Transform to multiply segments in parallel, achieving superlinear speedup for large integer multiplication while managing complexity through structured decomposition.
Solution Approach 2:
The patent replaces conventional mechanical multiplication algorithms with a transform-based approach using Fast Fourier Transform. This substitution enables multiplication to be performed in the frequency domain, achieving O(n log n) complexity instead of the traditional O(n^2) or O(n^1.58) complexity of schoolbook and Karatsuba methods.
2Productivity
If integers are represented in standard binary format, then hardware compatibility is maintained, but multiplication efficiency deteriorates for large numbers
Solution Approach 1:
The patent changes the representation parameter from standard binary to a customized radix representation where integers are expressed as arrays of log2(N)-bit chunks. This parameter change enables efficient multiplication through Fast Fourier Transform while maintaining compatibility with standard hardware through systematic conversion, achieving both efficiency and adaptability.
3Productivity
If existing FFT-based multiplication is used, then multiplication speed improves, but implementation complexity and constant factors increase
Solution Approach 1:
The patent segments the integer multiplication into manageable chunks of log2(N) bits, which simplifies the FFT implementation by reducing the size of transforms needed. This segmentation strategy lowers implementation complexity compared to applying FFT to full-length integers, while still achieving superlinear speedup for large numbers.
Solution Approach 2:
The patent applies partial FFT-based multiplication by processing only the significant portions of the integer representation. This partial action approach reduces the overhead of FFT operations on smaller chunks while maintaining overall efficiency, avoiding the excessive complexity of full-length FFT implementations.
Data Source
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AI summary
In an approach, a processor receives a plurality of first operand values, where the first operand values are integer values. A processor adds, using binary addition, the plurality of first operand values resulting in a sum value S. A processor determines a single combined modular correction term D for a binary sum of all operand values based on leading bits of the sum value S. A processor performs a modular addition of S and D resulting in a modular sum of said plurality of said first operand values.