Modular Multiplication Systolic Array Idle Time Reduction

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Solution Overview

Problem

Existing modular multiplication techniques in prime fields face performance degradation and idle-time issues due to broadcast structures and routing problems, particularly when processing a large number of bits in public key operations.

Innovation Solution

A modular multiplication apparatus employing a systolic structure with serial multipliers and serial squarer-based multipliers, utilizing a drain structure to process input sets efficiently and output results in digit-serial format, allowing immediate feedback and reducing idle time by merging cells and optimizing hardware usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a typical configuration with control signals broadcast to multiple registers is used, then public key operations can be performed, but performance is drastically degraded

Engineering Contradiction:
ImproveperformanceVSAvoidbroadcast structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The arithmetic unit is divided into multiple operational units arranged in a systolic array structure, where each unit performs specific multiplication operations. This segmentation eliminates the need for broadcast control signals by distributing operations across independent units that process data in a pipelined manner, thereby resolving the contradiction between performance and structural complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The systolic array employs dynamic data flow where intermediate results are immediately passed to subsequent stages without waiting for broadcast control. This dynamic operation allows continuous processing of multiple input sets, improving productivity while avoiding the static broadcast mechanism that causes performance degradation.

Inventive Principle:
Principle #15Dynamics

2Productivity

If conventional modular multiplication methods are used, then calculations can be performed, but idle stages are generated

Engineering Contradiction:
Improveprocessing efficiencyVSAvoididle time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The drain structure enables continuous processing by allowing new input sets to be loaded while previous calculations are still being processed. Multiple operational units work in parallel with overlapping execution stages, ensuring that no unit remains idle and maintaining continuous useful action throughout the computation process.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The system performs preliminary loading of input data into the systolic array before the actual multiplication is complete. Subsequent input sets are prepared and fed into the pipeline in advance, eliminating idle stages by ensuring that operational units always have data to process.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If broadcast structures are used for routing, then control can be simplified, but performance degradation occurs due to routing problems

Engineering Contradiction:
Improverouting controlVSAvoidperformance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

Each operational unit in the systolic array is self-sufficient, receiving its own control parameters and data independently without requiring broadcast signals from a central controller. The units autonomously perform their multiplication operations and pass results to the next stage, eliminating routing problems while maintaining ease of operation through localized decision-making.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10310817B2Apparatus and method for modular multiplication
Publication Date: 2019.06.04 ELECTRONICS & TELECOMM RES INST
  • US10310817B2 patent drawing
  • US10310817B2 patent drawing
  • US10310817B2 patent drawing

AI summary

An apparatus and method for modular multiplication. The modular multiplication apparatus includes a first operation unit for performing a first operation based on a structure of at least one of a serial multiplier and a serial squarer-based multiplier; a second operation unit for performing a second operation based on a structure of at least one of the serial multiplier and the serial squarer-based multiplier; an adder unit for outputting the sum of results of the first operation and the second operation, inputting an intermediate value stream to the first input unit, which calculates the product of the intermediate value stream and a zeta parameter, and outputting a High-Order Term as a result of Montgomery Modular Multiplication, wherein the first and second operation units output a result in digit-serial format in order from the least significant digit to the most significant digit.