Modular Multiplier Architecture for Fixed-Time Cryptographic Reduction

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Solution Overview

Problem

Current asymmetric cryptography algorithms, such as RSA, DSA, DH, ECDSA, and EdDSA, require computationally intensive modular multiplication operations that are either vulnerable to timing attacks or inefficient due to superfluous calculations, especially when using large integers.

Innovation Solution

A method for modular multiplication that uses a fixed set of parameters independent of the modulus value, allowing for parallel partial modular reduction and reducing the need for switching between domains, utilizing a single multiplier for efficient processing and fixed timing, and incorporating final modular reduction into the multiplier architecture.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional modular multiplication methods are used for large integers, then cryptographic security is maintained, but computation time increases and timing attacks become vulnerable

Engineering Contradiction:
Improvecryptographic securityVSAvoidcomputation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the modular multiplication operation into smaller manageable segments by processing integers in chunks of fixed digit size (e.g., 32-bit or 64-bit words). This segmentation allows parallel processing of multiple operations simultaneously, reducing overall computation time while maintaining security through the modular arithmetic properties that remain valid for the segmented approach.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent pre-computes and stores modular reduction coefficients and inverse modulus values before the actual multiplication operation. These pre-computed values are then used during the multiplication process to avoid repeated expensive division operations, thereby reducing computation time while preserving cryptographic security.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If modular multiplication is performed with variable timing based on input values, then computational efficiency may improve, but timing attacks become more vulnerable

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidtiming attack vulnerability
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent implements a dynamic computation path that adapts to different input values while maintaining constant overall timing. The algorithm uses conditional operations that select different computational paths based on input characteristics, but all paths are designed to complete in the same number of clock cycles, preventing timing attacks while optimizing for specific computational scenarios.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes computational parameters such as the number of iterations and operation types based on input value characteristics, while maintaining a fixed upper bound on execution time. This allows the system to optimize for particular cases (e.g., small results requiring fewer operations) without creating variable timing that could be exploited by timing attacks.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If a single multiplier architecture is used for all modular multiplication operations, then device complexity is reduced, but computational efficiency for large integers deteriorates

Engineering Contradiction:
Improvemultiplier architecture complexityVSAvoidcomputational efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent designs a universal modular multiplication architecture that can handle various integer sizes and cryptographic operations using the same basic hardware components. The multiplier is configured to process different digit sizes and operation types through software-controlled algorithms, eliminating the need for separate dedicated hardware circuits for each operation while maintaining high computational efficiency through parallel processing capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250258651A1Modular multiplier with improved efficiency
Publication Date: 2025.08.14 FORTIFYIQ INC
  • US20250258651A1 patent drawing
  • US20250258651A1 patent drawing
  • US20250258651A1 patent drawing

AI summary

A method for performing modular multiplication of a first multiplicand and a second multiplicand in a cryptographic engine, the method including calculating an integer corresponding with an inverse of a modulus based on a number of bits in the modulus, a digit size of the modular multiplier and a fixed size coefficient. The method also includes calculating a result of the modular multiplication using a plurality of modular reduction coefficients determined using the integer and respective digits of the multiplicands, the result less than an upper size limit that is based on the size coefficient and the modulus. The method further includes determining a final result of the modular multiplication based on a difference between the result and the modulus. If the difference is less than zero, the result is the final result, and if the difference is greater than or equal to zero, the difference is the final result.