Modular Multiplier Recoding for Lower-Delay Redundant Multiplication
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Solution Overview
Problem
Existing modular arithmetic units in RSA and ECC public key encryption algorithms face performance limitations due to the complexity of handling redundant-form multipliers, which increases delay and area complexity and requires significant hardware resources.
Innovation Solution
A multiplication method and modular multiplier design that transforms redundant-form multipliers using a recoding constant '1010 ... 1010' to simplify operations, reducing partial products and hardware requirements through bitwise operations and recoding techniques, such as full addition, half addition, and modified half addition, without converting to a non-redundant form.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional modular arithmetic units are used to handle redundant-form multipliers, then the multiplication operation can be performed, but the delay and area complexity increases significantly and hardware resources are consumed
Solution Approach 1:
The patent changes the parameter representation by introducing a recoding constant (1010...1010) to transform the redundant-form multiplier into a modified redundant form. This parameter transformation enables the multiplication to be performed with reduced hardware complexity while maintaining the same computational functionality, directly resolving the contradiction between multiplication speed and hardware complexity
Solution Approach 2:
The patent applies different processing methods to different parts of the multiplication operation. Specifically, it uses modified half-addition for certain bit positions and full-addition for others, optimizing the hardware structure locally to reduce overall complexity while maintaining multiplication performance
2Device complexity
If redundant-form multipliers are used directly without transformation, then the hardware structure can be simpler, but the calculation delay increases
Solution Approach 1:
The patent performs preliminary transformation of the redundant-form multiplier by adding the recoding constant before the main multiplication process. This preliminary action modifies the multiplier in advance to enable faster subsequent processing with simpler hardware, effectively reducing the calculation delay while maintaining structural simplicity
3Ease of manufacture
If full addition is used for transforming the redundant-form multiplier, then the transformation can be completed, but the area complexity and hardware resources increase
Solution Approach 1:
The patent segments the addition operation into modified half-addition and full-addition components, applying each to specific bit positions of the multiplier. This segmentation allows the transformation to be completed while using fewer hardware resources overall, as modified half-addition requires less area than full addition for each bit position
Data Source
AI summary
A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundant-form multiplier by adding a recoding constant to the multiplier, performing recoding by using the transformed multiplier, and performing partial multiplication between the multiplier and a multiplicand using result values of the recoding.